MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 241

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-15
Figure 6-19
Table 6-16
Freescale Semiconductor
Offset 0x2_0E40
Reset
1–26
Bits
W
27
28
29
30
31
R
0
MULL2ERR
MBECCERR Multiple-bit ECC error (bit reset, write 1 to clear)
SBECCERR Single-bit ECC error (bit reset, write 1 to clear)
MULL2ERR Multiple L2 errors (bit reset, write 1 to clear)
L2CFGERR L2 configuration error (bit reset, write 1 to clear)
W1c
TPARERR
0
describes L2CAPTECC fields.
describes L2ERRDET fields.
Name
shows the L2 error detect register (L2ERRDET).
—
—
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
24–31 ECCCHKSUM The data path ECC of the failing double word
8–23
Bits
0–7
0 Multiple L2 errors of the same type were not detected
1 Multiple L2 errors of the same type were detected
Reserved
Tag parity error (bit reset, write 1 to clear)
0 Tag parity error was not detected
1 Tag parity error was detected
Note that if an L2 cache tag parity error occurs on an attempt to write a new line, the L2 cache must
be Flash invalidated. L2 functionality is not guaranteed if Flash invalidation is not performed after a
tag parity error.
0 Multiple-bit ECC errors were not detected
1 Multiple-bit ECC errors were detected
0 Single-bit ECC error was not detected
1 Single-bit ECC error was detected.
Reserved
0 L2 configuration errors were not detected
1 L2 illegal configuration error detected. Reports inconsistencies between the L2SRAM,
L2STASHDIS and L2STASHCTL fields of the L2 control register (L2CTL)
ECCSYND
Figure 6-19. L2 Error Detect Register (L2ERRDET)
Name
—
Table 6-15. L2CAPTECC Field Descriptions
Table 6-16. L2ERRDET Field Descriptions
—
The calculated ECC syndrome of the failing double word
Reserved
All zeros
Description
Description
26
TPARERR MBECCERR SBECCERR
w1c
27
w1c
28
L2 Look-Aside Cache/SRAM
w1c
29
Access: W1c
30
—
L2CFGDIS
w1c
31
6-21