MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1476

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.8.6.3
Error interrupts will be least frequent and should be placed last in the interrupt service routine.
21.9
The host mode operation of the USB DR module is nearly EHCI-compatible with few minor differences.
For the most part, the module conforms to the data structures and operations described in Section 3, “Data
Structures,” and Section 4, “Operational Model,” in the EHCI specification. The particulars of the
deviations occur in the following areas:
21.9.1
The USB module supports directly connected full and low speed devices without requiring a companion
controller by including the capabilities of a USB 2.0 high speed hub transaction translator. Although there
is no separate transaction translator block in the system, the transaction translator function normally
associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The
embedded transaction translator function is an extension to EHCI interface, but makes use of the standard
data structures and operational models that exist in the EHCI specification to support full and low speed
devices.
21-142
USB Error Interrupt
System Error
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•
•
Interrupt
Embedded transaction translator—Allows direct attachment of FS and LS devices in host mode
without the need for a companion controller.
Device operation—In host mode, the device operational registers are generally disabled and thus
device mode is mostly transparent when in host mode. However, there are a couple exceptions
documented in the following sections.
Embedded design interface—The module does not have a PCI interface and therefore the PCI
configuration registers described in the EHCI specification are not applicable.
Port Change
Sleep Enable (Suspend)
Reset Received
Deviations from the EHCI Specifications
Embedded Transaction Translator Function
Error Interrupts
Interrupt
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD
will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt
(w/ ENDPTCOMPLETE).
Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD.
Table 21-93. Low Frequency Interrupt Events
Change software state information.
Change software state information. Low power handling as necessary.
Change software state information. Abort pending transfers.
Table 21-94. Error Interrupt Events
Action
Action
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