MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1268

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19.5.1.3
This state machine is responsible for frame reception from the PHY layer. The state machine removes the
SOF and EOF headers and other primitives from each frame, calculates the CRC, and compares it to the
received CRC. Between the SOF and CRC markers, the link layer accepts the current word from the Phy
layer and uses this as the next word of the frame, transferring it to the transport layer. At the end of the
frame reception, if the calculated CRC is not the same as the received CRC, the link layer signals an error
to the transport layer. This is done via RX_CRC_OK and RX_CRC_NOT_OK. During frame reception,
if no errors are detected, the link layer transmits R_IP primitives to the far end peer link layer. Finally, at
the end of the frame reception, the link layer sends the R_OK primitive if no error was detected during
reception. If an error was detected, it sends a R_ERR primitive instead.
The receive state machine also partakes in flow control actions if necessary, during FIS reception. If the
transport layer cannot accept a new word, (because its receive FIFO has reached its watermark level), and
the FIS is not finished, the receive state machine responds by sending HOLD primitives on the back
channel until such time as the transport layer is ready to accept FIS data again. Also, during FIS reception,
if the state machine detects a received HOLD primitive from the far end, it responds by sending HOLDA
primitives to the far end.
The current frame reception can be interrupted if the transport layer wishes to send a control register frame,
signaled via TRANSMIT_CRF.
If at any point in the frame reception process, the link layer detects error conditions, it signals these to the
command layer. The errors can occur if the link layer detects the following conditions:
19.5.1.4
This state machine is responsible for handling change of power mode requests. These requests can come
from the command layer superset registers or the far end. This state machine responds by transmitting
PMREQ_P/PMREQ_S primitives to the far end and waiting for PMACK primitives from it in response.
Once PMACK is received, the state machine instructs the PHY layer to enter either a partial or slumber
state.
A write to the SControl register SPM field or reception of a COMWAKE from the far end will initiate a
resume to active power mode.
If the link layer receives a PMREQ_P/PMREQ_S primitive from a peer link layer and is enabled to
perform power management modes (SControl IPM bits are cleared), it responds by sending at least four
PMACK primitives. A write to the SControl register SPM field or reception of a COMWAKE from the far
end will initiate a resume to active power mode.
19-38
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PHY_READY negates
SYNC primitive is received during frame transmission
PHY_READY negates
SYNC primitives is received during frame transmission
WTRM primitive is received before EOF
Receive State Machine
Power Mode Change State Machine
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor