MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 57

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 8-29
DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)...................... 8-29
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) ................................ 8-30
DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 8-33
DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 8-33
DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)....... 8-34
DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 8-35
DDR Initialization Extended Address Configuration Register
DDR SDRAM Timing Configuration 4 Register (TIMING_CFG_4).................................. 8-36
DDR SDRAM Timing Configuration 5 Register (TIMING_CFG_5).................................. 8-37
DDR ZQ Calibration Control Register (DDR_ZQ_CNTL) ................................................. 8-39
DDR Write Leveling Control Register (DDR_WRLVL_CNTL) ......................................... 8-40
DDR Self Refresh Counter Register (DDR_SR_CNTR) ..................................................... 8-43
DDR Register Control Word 1 (DDR_SDRAM_RCW_1) .................................................. 8-44
DDR Register Control Word 2 (DDR_SDRAM_RCW_2) .................................................. 8-45
DDR Debug Status Register 1 (DDRDSR_1)....................................................................... 8-46
DDR Debug Status Register 2 (DDRDSR_2)....................................................................... 8-47
DDR Control Driver Register 1 (DDRCDR_1) .................................................................... 8-49
DDR Control Driver Register 2 (DDRCDR_2) .................................................................... 8-50
DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 8-50
DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 8-51
Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI) ......... 8-51
Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)......... 8-52
Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)............................ 8-52
Memory Data Path Read Capture High Register (CAPTURE_DATA_HI).......................... 8-53
Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO) ......................... 8-54
Memory Data Path Read Capture ECC Register (CAPTURE_ECC)................................... 8-54
Memory Error Detect Register (ERR_DETECT) ................................................................. 8-55
Memory Error Disable Register (ERR_DISABLE).............................................................. 8-56
Memory Error Interrupt Enable Register (ERR_INT_EN)................................................... 8-57
Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)........................... 8-58
Memory Error Address Capture Register (CAPTURE_ADDRESS) ................................... 8-58
Memory Error Extended Address Capture Register (CAPTURE_EXT_ADDRESS).......... 8-59
Single-Bit ECC Memory Error Management Register (ERR_SBE) .................................... 8-59
DDR Memory Controller Block Diagram ............................................................................ 8-61
Typical Dual Data Rate SDRAM Internal Organization....................................................... 8-62
Typical DDR SDRAM Interface Signals .............................................................................. 8-62
Example 256-Mbyte DDR SDRAM Configuration With ECC ............................................ 8-63
DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 8-74
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 8-75
(DDR_INIT_EXT_ADDR).............................................................................................. 8-35
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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