MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 27

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
14.5.3.11.7
14.5.3.11.8
14.5.3.11.9
14.5.3.11.10
14.5.3.11.11
14.5.3.11.12
14.5.3.11.13
14.5.3.11.14
14.5.4
14.5.4.1
14.5.4.1.1
14.5.4.1.2
14.5.4.1.3
14.5.4.2
14.5.4.2.1
14.5.4.2.2
14.5.4.3
14.5.4.3.1
14.5.4.3.2
14.5.4.3.3
14.5.4.3.4
14.5.4.3.5
14.5.4.3.6
14.5.4.3.7
14.5.4.3.8
14.5.4.3.9
14.5.4.3.10
14.6
14.6.1
14.6.1.1
14.6.1.2
14.6.1.3
14.6.1.4
14.6.1.5
14.6.1.6
14.6.1.7
14.6.1.8
14.6.2
14.6.2.1
14.6.2.2
14.6.2.3
Freescale Semiconductor
Functional Description............................................................................................... 14-146
Ten-Bit Interface (TBI) .......................................................................................... 14-133
Connecting to Physical Interfaces on Ethernet ...................................................... 14-146
Connecting to FIFO Interfaces .............................................................................. 14-156
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TBI Transmit Process ........................................................................................ 14-134
TBI Receive Process.......................................................................................... 14-134
TBI MII Set Register Descriptions .................................................................... 14-135
Media-Independent Interface (MII) ................................................................... 14-146
Reduced Media-Independent Interface (RMII) ................................................. 14-146
Gigabit Media-Independent Interface (GMII) ................................................... 14-148
Reduced Gigabit Media-Independent Interface (RGMII) ................................. 14-148
Ten-Bit Interface (TBI)...................................................................................... 14-149
Reduced Ten-Bit Interface (RTBI) .................................................................... 14-150
Ethernet Physical Interfaces Signal Summary................................................... 14-152
SGMII Interface................................................................................................. 14-156
Flow Control...................................................................................................... 14-157
CRC Appending and Checking ......................................................................... 14-157
8-Bit GMII-Style Packet FIFO Mode................................................................ 14-158
Timer Counter Register (TMR_CNT_H/L)................................................... 14-128
Timer Drift Compensation Addend Register (TMR_ADD).......................... 14-129
Timer Accumulator Register (TMR_ACC)................................................... 14-130
Timer Prescale Register (TMR_PRSC)......................................................... 14-130
Timer Offset Register (TMROFF_H/L) ........................................................ 14-131
Alarm Time Comparator Register (TMR_ALARM1–2_H/L) ...................... 14-131
Timer Fixed Interval Period Register (TMR_FIPER1–3) ............................. 14-132
External Trigger Stamp Register (TMR_ETTS1–2_H/L) ............................. 14-133
Packet Encapsulation ..................................................................................... 14-134
8B10B Encoding............................................................................................ 14-134
Preamble Shortening...................................................................................... 14-134
Synchronization ............................................................................................. 14-134
Auto-Negotiation for 1000BASE-X.............................................................. 14-135
Control Register (CR).................................................................................... 14-136
Status Register (SR)....................................................................................... 14-137
AN Advertisement Register (ANA) .............................................................. 14-138
AN Link Partner Base Page Ability Register (ANLPBPA)........................... 14-140
AN Expansion Register (ANEX) .................................................................. 14-141
AN Next Page Transmit Register (ANNPT).................................................. 14-141
AN Link Partner Ability Next Page Register (ANLPANP) .......................... 14-142
Extended Status Register (EXST) ................................................................. 14-143
Jitter Diagnostics Register (JD) ..................................................................... 14-144
TBI Control Register (TBICON)................................................................... 14-145
Contents
Title
Number
Page
xxvii