MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 714

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
13.4.3.4
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
When the core begins accessing memory after system reset, LCS0 is asserted initially to load a 4-Kbyte
boot block into the FCM buffer RAM, but core instruction fetches occur from the buffer RAM.
13.4.3.4.1
The boot chip-select also provides a programmable port size, which is configured during reset. The boot
chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it
can be used as any other chip-select register after the preferred address range is loaded into BR0. After the
first write to OR0, the boot chip-select can be restarted only with a hardware reset.
the initial values of the boot bank in the memory controller.
13-72
FCM Boot Chip-Select Operation
FCM Bank 0 Reset Initialization
Table 13-38. Boot Bank Field Values after Reset for FCM as Boot Controller
Register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
BR0
LCLK
(unused)
LALE
(unused)
LCS n
LFCLE/
LFALE
LFRE
LAD[0:7]
TA
Figure 13-59. FCM Read Data Timing with Extended Hold Time
DECC
MSEL
ATOM
Field
WP
(for TRLX = 0, EHTR = 1, RST = 1, SCY = 1)
BA
PS
V
Notes:
t
t
RC
EHTR
= Read data cycle time.
read cycle
= Extended read data hold time.
last read data
t
RC
0000_0000_0000_0000_0
From cfg_rom_loc
Setting
001
00
0
0
t
EHTR
Table 13-38
Freescale Semiconductor
describes