MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1468

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.8.3.6
Isochronous endpoints are used for real-time scheduled delivery of data and their operational model is
significantly different than the host throttled Bulk, Interrupt, and Control data pipes. Real time delivery by
the USB controller will is accomplished by the following:
The USB controller in host mode uses the periodic frame list to schedule data exchanges to Isochronous
endpoints. The operational model for device mode does not use such a data structure. Instead, the same
dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints. The difference is
in the handling of the dTD.
The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a delayed
operation such that an endpoint will become primed only after a SOF is received. After the DCD writes
the prime bit, the prime bit will be cleared as usual to indicate to software that the device controller
completed a priming the dTD for transfer. Internal to the design, the device controller hardware masks that
prime start until the next frame boundary. This behavior is hidden from the DCD but occurs so that the
device controller can match the dTD to a specific (micro) frame.
Another difference with isochronous endpoints is that the transaction must wholly complete in a
(micro)frame. Once an ISO transaction is started in a (micro)frame it will retire the corresponding dTD
when MULT transactions occur or the device controller finds a fulfillment condition.
21-134
•
•
•
Exactly MULT Packets per (micro)Frame are transmitted/received. Note: MULT is a two-bit field
in the device Queue Head. The variable length packet protocol is not used on isochronous
endpoints.
NAK responses are not used. Instead, zero length packets and sent in response to an IN request to
an unprimed endpoints. For unprimed RX endpoints, the response to an OUT transaction is to
ignore the packet within the device controller.
Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If the
ISO-dTD is still active after that frame, then the ISO-dTD will be held ready until executed or
canceled by the DCD.
1
2
3
Isochronous Endpoint Operational Model
SYSERR—System error should never occur when the latency FIFOs are correctly sized and
the DCD is responsive.
Force Bit Stuff Error.
NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the
USB variable length protocol then ACK.
Invalid
Token
Type
Ping
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-88. Control Endpoint Bus Response Matrix (continued)
STALL
Ignore
Stall
Primed
Ignore
NAK
Not
Endpoint State
Primed
Ignore
ACK
Underflow
Ignore
N/A
Overflow
Ignore
N/A
Lockout
Ignore
Setup
Freescale Semiconductor
N/A