MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 713

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The timing parameters are summarized in
13.4.3.3.5
Allowance for slow output driver turn-off when reading NAND Flash EEPROMs is made via setting of
ORn[EHTR] and ORn[TRLX]. The extended read data hold time, shown at t
Figure
(requiring LALE assertion). LCSn is negated during t
time to disable their drivers.
Freescale Semiconductor
LCLK
(unused)
LFWE
LFCLE/
LFALE
LFRE
LAD[0:7]
TA
13-59, is a delay inserted by FCM between the last data read and another eLBC memory access
write cycle
write data
FCM Extended Read Hold Timing
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Notes:
Option Register
TRLX
In the parameters, SCY refers to a delay of OR n [SCY] clock cycles.
0
0
1
1
Attributes
t
t
t
RP
RHT
WRT
RST
Table 13-37. FCM Read Data Timing Parameters
= LFRE pulse time, read period.
0
1
0
1
= LFRE hold time.
= Write to read turnaround time.
Figure 13-58. FCM Read Data Timing
½+2×SCY
1+2×SCY
¾+SCY
(for TRLX = 0, RST = 0, SCY = 1)
1+SCY
t
RP
Table
Timing Parameter (LCLK Clock Cycles)
write-to-read turnaround
t
WRT
t
13-37.
RHT
1
1
2
2
EHTR
2×SCY
2×SCY
SCY
SCY
t
to allow external devices and bus transceivers
WS
t
t
WS
RC
= Read data cycle time.
= Read wait state time.
3+2×SCY 8×(2+SCY)
3+2×SCY 8×(2+SCY)
2+SCY
2+SCY
t
RC
4×(2+SCY)
4×(2+SCY)
EHTR
1
read cycle
t
WRT
t
RP
Enhanced Local Bus Controller
read data
t
t
WS
RC
in
Figure 13-47
t
RHT
sample data
and
13-71