MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 103

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table
Number
21-38
21-39
21-40
21-41
21-42
21-43
21-44
21-45
21-46
21-47
21-48
21-49
21-50
21-51
21-52
21-53
21-54
21-55
21-56
21-57
21-58
21-59
21-60
21-61
21-62
21-63
21-64
21-65
21-66
21-67
21-68
21-69
21-70
21-71
21-72
21-73
21-74
21-75
21-76
21-77
21-78
Freescale Semiconductor
Next Schedule Element Pointer .......................................................................................... 21-45
iTD Transaction Status and Control.................................................................................... 21-46
Buffer Pointer Page 0 (Plus) ............................................................................................... 21-46
iTD Buffer Pointer Page 1 (Plus) ........................................................................................ 21-47
Buffer Pointer Page 2 (Plus) ............................................................................................... 21-47
Buffer Pointer Page 3–6 ...................................................................................................... 21-47
Next Link Pointer................................................................................................................ 21-48
Endpoint and Transaction Translator Characteristics ......................................................... 21-48
Micro-Frame Schedule Control .......................................................................................... 21-49
siTD Transfer Status and Control........................................................................................ 21-49
siTD Buffer Pointer Page 0 (Plus) ...................................................................................... 21-50
siTD Buffer Pointer Page 1 (Plus) ...................................................................................... 21-51
siTD Back Link Pointer ...................................................................................................... 21-51
qTD Next Element Transfer Pointer (DWord 0) ................................................................. 21-52
qTD Alternate Next Element Transfer Pointer (DWord 1) ................................................. 21-52
qTD Token (DWord 2) ........................................................................................................ 21-53
qTD Buffer Pointer ............................................................................................................. 21-56
Queue Head DWord 0 ......................................................................................................... 21-57
Endpoint Characteristics: Queue Head DWord 1................................................................ 21-58
Endpoint Capabilities: Queue Head DWord 2 .................................................................... 21-58
Current qTD Link Pointer ................................................................................................... 21-59
Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9) ................................... 21-60
FTSN Normal Path Pointer ................................................................................................. 21-61
FSTN Back Path Link Pointer ............................................................................................ 21-61
Default Values of Operational Register Space.................................................................... 21-62
Behavior During Wake-up Events ...................................................................................... 21-65
Operation of FRINDEX and SOFV (SOF Value Register)................................................. 21-69
Example Periodic Reference Patterns for Interrupt Transfers ............................................ 21-82
Ping Control State Transition Table .................................................................................... 21-83
Interrupt IN/OUT Do Complete Split State Execution Criteria.......................................... 21-97
Initial Conditions for OUT siTD TP and T-Count Fields ................................................. 21-105
Transaction Position (TP)/Transaction Count (T-Count) Transition Table....................... 21-105
Summary siTD Split Transaction State............................................................................. 21-109
Example Case 2a—Software Scheduling siTDs for an IN Endpoint................................ 21-110
Summary of Transaction Errors ........................................................................................ 21-113
Summary Behavior on Host System Errors ...................................................................... 21-116
Endpoint Capabilities/Characteristics ............................................................................... 21-118
Current dTD Pointer.......................................................................................................... 21-119
Multiple Mode Control ..................................................................................................... 21-120
Next dTD Pointer .............................................................................................................. 21-120
dTD Token ........................................................................................................................ 21-121
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Tables
Title
Number
Page
ciii

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