MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 563

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The mode register is cleared when the MDEU is reset or re-initialized. Setting a reserved mode bit
generates a data error. If the mode register is modified during processing, a context error is generated.
Table 10-59
Freescale Semiconductor
Reset
Field
Addr
R/W
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
52-53
0–50
Bits
51
54
55
56
57
58
0
describes MDEU Mode Register fields in old configuration.
—
NEW (=0)
MDEU_B
CONT
SMAC
Name
CICV
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
50
MDEU_B
Figure 10-83. MDEU Mode Register in Old Configuration
Table 10-59. MDEU Mode Register in Old Configuration
Reserved
Selects which algorithms are enabled by the ALG bits.
0 MDEU-A enables selection between SHA-1, SHA-256, MD5, and SHA-224
1 MDEU-B enables selection between SHA-384, SHA-256, SHA-512, and SHA-224.
Reserved, must be cleared.
Determines the configuration of the MDEU Mode Register. This table shows the
configuration for NEW=0.
Reserved, must be cleared.
Continue: Most operations require this bit to be cleared. It is set only when the data to be
hashed is spread across multiple descriptors.
The value programmed in PD must be opposite to the value in this bit.
0 Do autopadding and complete the message digest. Used when the entire hash is
1 This hash is continued in a subsequent descriptor. Do not autopad and do not complete
Compare Integrity Check Values:
0 Normal operation; no ICV checking.
1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input
Only applicable to descriptor types that provide for reading an ICV in value.
Specifies whether to perform an SSL-MAC operation:
0 Normal operation
1 Perform an SSL3.0 MAC operation. This requires a key and key length. If this is set then
51
performed with one descriptor, or on the last of a sequence of descriptors.
the message digest.
FIFO. If the ICVs do not match, send an error interrupt to the channel. The number of
bytes to be compared is given by the ICV size register.
the HMAC bit should be 0.
52
—
53
NEW=0
MDEU 0x3_6000
54
R/W
0
55
—
Description
CONT CICV SMAC INIT HMAC PD
56
57
58
59
Security Engine (SEC) 3.0
60
61
62
ALG
10-133
63