MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1191

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.10.17 PCI Express Subsystem Vendor ID Update Register (EP Mode
The PCI Express subsystem vendor ID update register, shown in
for the Subsystem ID and Subsystem Vendor ID registers in the Type 0 configuration header.
The fields of the PCI Express subsystem vendor ID update register are described in
When used as an endpoint, the controller’s initialization software programs the desired subsystem ID and
subsystem vendor ID values in PEX_SSVID_UPDATE before setting the CFG_READY bit in the
PEX_CFG_READY register (see
way, when the host begins system enumeration, the correct values are present in the Type 0 configuration
header.
17.3.10.18 Configuration Ready Register—0x4B0
The PCI Express configuration ready register, shown in
complete status to the transaction layer. The transaction layer handles configuration requests from external
hosts only after the CFG_READY bit is set. All the configuration requests received from external hosts
before the CFG_READY bit is set are completed with configuration request retry status (CRS). The
CFG_READY bit in this register should be set after all relevant configuration registers have been
programmed. This makes sure the external host reads the correct capability advertisements during
enumeration.
Note that the state of PEX_CFG_READY[CFG_READY] is dependent upon the POR configuration
setting described in
Freescale Semiconductor
31–16
15–0
Bits
Offset 0x4B0
Reset
Offset 0x478 (EP-mode only)
Reset
W
R
W
R
31
31
Figure 17-118. PCI Express Subsystem Vendor ID Update Register (PEX_SSVID_UPDATE)
SSV_ID
SS_ID
Name
Only)—0x478
Figure 17-119. PCI Express Configuration Ready Register (PEX_CFG_READY)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 17.5.1, “Boot Mode and Inbound Configuration
Table 17-115. PEX_SSVID_UPDATE Field Descriptions
Subsystem ID [15–0] value
Subsystem vendor ID [15–0] value
SS_ID
Section 17.3.10.18, “Configuration Ready
0000_000 n (defined during POR)
—
All zeros
16 15
Figure
Description
17-119, is used to indicate configuration
Figure
17-118, is used to set the values
SSV_ID
Transactions.”
Register—0x4B0”). That
PCI Express Interface Controller
Table
Access: Read/Write
Access: Read/Write
1
17-115.
CFG_READY
0
17-95
0