MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1642

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
Complete List of Configuration, Control, and Status Registers
A.1.17
A-30
eTSEC3 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_6000 to 0x2_6FFF.
1
The addresses following 0x044, except 0x050, 0x0FC and 0x40C, are reserved and read as all 0s. Writes to these
registers are ignored.
0x044
0x0FC
Offset
0x00C
0x01C
0x02C
0x03C
0x40C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x028
0x030
0x034
0x038
0x040
0x050
1
eSDHC Registers
DMA system address (DSADDR)
Block attributes (BLKATTR)
Command argument (CMDARG)
Command transfer type (XFERTYP)
Command response0 (CMDRSP0)
Command response1 (CMDRSP1)
Command response2 (CMDRSP2)
Command response3 (CMDRSP3)
Data buffer access port (DATPORT)
Present state (PRSSTAT)
Protocol control (PROCTL)
System control (SYSCTL)
Interrupt status (IRQSTAT)
Interrupt status enable (IRQSTATEN)
Interrupt signal enable (IRQSIGEN)
Auto CMD12 status (AUTOC12ERR)
Host controller capabilities (HOSTCAPBLT)
Watermark level (WML)
Force event (FEVT)
Host controller version (HOSTVER)
DMA control register (DCR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
eSDHC Registers—Block Base Address 0x2_E000
Register
Table 1-3. eSDHC Memory Map
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
W
R
R
R
R
R
R
R
R
0xFF80_0000
0x117F_013F
0x01E3_0000
0x0000_0008
0x0000_0008
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0020
0x0000_8000
0x0000_0000
0x0000_0000
0x0000_0000
0x0010_0010
0x0000_0000
0x0000_0001
0x0000_0000
Reset
Freescale Semiconductor
Section/Page
20.4.10/20-22
20.4.11/20-26
20.4.12/20-29
20.4.13/20-31
20.4.14/20-33
20.4.15/20-34
20.4.16/20-34
20.4.17/20-36
20.4.18/20-37
20.4.5/20-11
20.4.5/20-11
20.4.5/20-11
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20.4.6/20-12
20.4.7/20-13
20.4.8/20-17
20.4.9/20-19
20.4.1/20-6
20.4.2/20-6
20.4.3/20-7
20.4.4/20-8