MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 539

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the DEU is used through channel-controlled access,
which means that most reads and writes of DEU registers are directed by the SEC channels. Driver
software would perform host-controlled register accesses only on a few registers for initial configuration
and error handling.
10.7.4.1
The DEU mode register contains 3 bits which are used to program DEU operation.
The mode register is cleared when the DEU is reset or re-initialized. Setting a reserved mode bit generates
a data error. If the mode register is modified during processing, a context error is generated.
Table 10-46
Freescale Semiconductor
Offset 0x3_2000
Reset
W
R
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 field of the descriptor header.
56–59
60–61
0–55
Bits
0
62
63
describes DEU mode register fields.
DEU Mode Register
Name
CM
ED
TS
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Reserved
Cipher Mode: Used to define the mode of DEU operation. See
combinations.
Triple/Single DES. If set, DEU operates the Triple DES algorithm; if not set, DEU operates
the single DES algorithm.
0 Single DES
1 Triple DES
Encrypt/decrypt. If set, DEU operates the encryption algorithm; if not set, DEU operates
the decryption algorithm.
0 Perform decryption
1 Perform encryption
Table 10-46. DEU Mode Register Field Descriptions
Figure 10-56. DEU Mode Register
Table 10-47. DEU Cipher Modes
Mode
ECB
CBC
—
All zeros
Description
CM (60:61)
00
01
Table 10-47
Security Engine (SEC) 3.0
Access: Read/Write
for mode bit
59
60 61 62
CM
TS ED
10-109
63