MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1316

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
when system access of the buffer catches up, the clock gate of this module is open and the SD clock is
active again.
20.5.3.3
The command agent deals with the transactions on SDHC_CMD line. See
the structure for the command CRC shift register.
The CRC polynomials for the SDHC_CMD are as follows:
20.5.3.4
The data agent handles the transactions on the eight data lines. Moreover, this module also detects the busy
state from on SDHC_DAT[0] line, and generates read wait state by the request from the transceiver. The
CRC polynomials for the SDHC_DAT are as follows:
20.5.4
This module controls all the reset signals within the eSDHC. There are four types of reset signals within
eSDHC: hardware reset, software reset for all, software reset for data, and software reset for command.
All these signals are fed into this module and stable signals are generated inside the module to reset all
other modules.
This module also gates off all the inside signals. The module monitors the activities of all other modules,
supplies the clocks for them, and when enabled, automatically gates off the corresponding clocks.
20-42
CRC_IN
CLR_CRC
ZERO
Generator polynomial: G(x) = x
M(x) = (first bit) x
CRC[6:0] = Remainder [(M(x) x
Generator polynomial: G(x) = x
M(x) = (first bit) x
CRC[15:0] = Remainder [(M(x) x
Clock & Reset Manager
Command Agent
Data Agent
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
CRC
Bus
[0]
n
n
+ (second bit) x
+ (second bit) x
Figure 20-23. Command CRC Shift Register
CRC
Bus
[1]
7
16
+ x
+ x
7
) G(x)]
16
CRC
Bus
3
[2]
12
) G(x)]
+ 1
n-1
n-1
+ x
+...+ (last bit) x
+...+ (last bit) x
5
+ 1
CRC_OUT
CRC
Bus
[3]
0
0
Figure 20-23
CRC
Bus
[4]
Freescale Semiconductor
CRC
Bus
for illustration of
[5]
CRC
Bus
[6]