MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1402

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
boundaries. The phase shift eliminates the beginning of frame and frame-wrap scheduling boundary
conditions.
The implementation of this phase shift requires that the host controller use one register value for accessing
the periodic frame list and another value for the frame number value included in the SOF token. These two
values are separate, but tightly coupled. The periodic frame list is accessed via the Frame List Index
Register (FRINDEX). Bits FRINDEX[2–0], represent the micro-frame number. The SOF value is coupled
to the value of FRINDEX[13–3]. Both FRINDEX[13–3] and the SOF value are incremented based on
FRINDEX[2–0]. It is required that the SOF value be delayed from the FRINDEX value by one
micro-frame. The one micro-frame delay yields a host controller periodic schedule and bus frame
boundary relationship as illustrated in
the periodic start and complete-split transactions for full-and low-speed periodic endpoints, using the
natural alignment of the periodic schedule interface.
Figure 21-45
frame boundaries. To aid the presentation, two terms are defined. The host controller's view of the
1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries
is called B-Frames.
H-Frame boundaries for the host controller correspond to increments of FRINDEX[13–3]. Micro-frame
numbers for the H-Frame are tracked by FRINDEX[2–0]. B-Frame boundaries are visible on the
high-speed bus via changes in the SOF token's frame number. Micro-frame numbers on the high-speed bus
are only derived from the SOF token's frame number (that is, the high-speed bus will see eight SOFs with
the same frame number value). H-Frames and B-Frames have the fixed relationship (that is, B-Frames lag
H-Frames by one micro-frame time) illustrated in
naturally aligned to H-Frames. Software schedules transactions for full- and low-speed periodic endpoints
relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly the right
time for the USB 2.0 hub periodic pipeline. As described in
(FRINDEX),”
which lags the FRINDEX register bits [13–3] by one micro-frame count.
required relationship between the value of FRINDEX and the value of SOFV. This lag behavior can be
21-68
Micro-Frames
HC Periodic
Figure 21-45. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries
Schedule
HS Bus
Frames
illustrates how periodic schedule data structures relate to schedule frame boundaries and bus
the SOF Value can be implemented as a shadow register (in this example, called SOFV),
7
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
SS
HC Periodic Schedule
Frame Boundaries
1
Full/Low-Speed
Interface Data Structure
Transaction
2
CS
H-Frame N
3
CS
Figure
B-Frame N
4
CS
5
CS
21-45. This adjustment allows software to trivially schedule
6
Figure
7
0
SS
21-45. The host controller's periodic schedule is
Section 21.3.2.4, “Frame Index Register
1
Full/Low-Speed
Interface Data Structure
Transaction
HS/FS/LS Bus
Frame Boundaries
2
CS
H-Frame N+1
3
CS
B-Frame N+1
Table 21-64
4
CS
5
CS
6
Freescale Semiconductor
illustrates the
7
0
1
2