MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 298

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-13
8-24
11–12
Bits
5–7
8–9
10
13
0
1
2
3
4
SDRAM_TYPE
DYN_PWR
MEM_EN
ECC_EN
RD_EN
describes the DDR_SDRAM_CFG fields.
SREN
Name
8_BE
DBW
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 SDRAM interface logic is disabled.
1 SDRAM interface logic is enabled. Must not be set until all other memory configuration
0 SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is
1 SDRAM self refresh is enabled during sleep.
causes the core to generate a machine check interrupt unless it is disabled (by clearing
HID1[RFXE]). If RFXE is zero and this error occurs, ERR_DISABLE[MBED] and
ERR_INT_EN[MBEE] must be zero and ECC_EN must be one to ensure an interrupt is generated.
See
e500 Core Family Reference Manual for further details.
0 No ECC errors are reported. No ECC interrupts are generated.
1 ECC is enabled.
0 Indicates unbuffered DIMMs.
1 Indicates registered DIMMs.
Note: RD_EN and 2T_EN must not both be set at the same time.
Reserved
initialization sequence to DRAM through Mode Register Set and Extended Mode Register Set
commands.
000–001Reserved
010 Reserved
011 DDR2 SDRAM
100 Reserved
101 Reserved
110 Reserved
111 DDR3 SDRAM
Reserved
0 Dynamic power management mode is disabled.
1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the
DRAM data bus width.
00
01
10
11
0 4-beat bursts are used on the DRAM interface.
1 8-beat bursts are used on the DRAM interface.
Note: DDR2 (SDRAM_TYPE = 011) must use 4-beat bursts, even when using 32-bit bus mode;
DDR SDRAM interface logic enable.
Self refresh enable (during sleep).
ECC enable. Note that uncorrectable read errors may cause the assertion of core_fault_in , which
Registered DIMM enable. Specifies the type of DIMM used in the system.
Type of SDRAM device to be used. This field is used when issuing the automatic hardware
Dynamic power management mode
8-beat burst enable.
parameters have been appropriately configured by initialization code.
responsible for preserving the integrity of SDRAM during sleep.
SDRAM CKE signal is negated.
Section 5.2, “e500 Core Integration and the Core Complex Bus
64-bit bus is used
32-bit bus is used
Reserved
Reserved
Table 8-13. DDR_SDRAM_CFG Field Descriptions
DDR3 (SDRAM_TYPE = 111) must use 8-beat bursts when using 32-bit bus mode
Description
(CCB),” and the PowerPC™
Freescale Semiconductor