MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 542

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.4.5
This status register, displayed in
signals. The DEU status register is read only. Writing to this location results in address error being reflected
in the DEU interrupt status register.
Table 10-50
10-112
Offset 0x3_2028
Reset
40-47
48-55
56-57
59-60
0–39
Bits
W
58
61
62
63
R
0
describes the DEU status register’s bit settings.
DEU Status Register
Name
HALT
OFL
IFL
RD
—
—
—
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
Halt. Indicates that the DEU has halted due to an error.
0 DEU not halted
1 DEU halted
Note: Because the error causing the DEU to stop operating may be masked before reaching
Reserved
Error interrupt: This status bit reflects the state of the error interrupt signal, as sampled by
the controller interrupt status register
0 DEU is not signaling error
1 DEU is signaling error
Done interrupt: This status bit reflects the state of the done interrupt signal, as sampled by
the controller interrupt status register
0 DEU is not signaling done
1 DEU is signaling done
Reset done. This status bit, when high, indicates that DEU has completed its reset
sequence, as reflected in the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the
the interrupt status register, the DEU interrupt status register is used to provide a
second source of information regarding errors preventing normal operation.
register, indicating the EU is ready for operation.
Figure
Figure 10-60. DEU Status Register
Table 10-50. DEU Status Register
39 40
10-60, contains 6 fields which reflect the state of DEU internal
OFL
47 48
All zeros
IFL
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
55
Description
56
—
57
HALT
58
59
—
Freescale Semiconductor
60
Access: Read only
EI
61
(ISR)”).
(ISR)”).
DI
62
RD
63