MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 270

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

e500 Coherency Module
7.2.1.8
The ECM error low address capture register (EELADR) is shown in
Table 7-9
7-8
Offset 0x0_1E10
Reset
11–15
17–20
21–30
Bits
W
16
31
R
0–31
Bits
0
describes EELADR fields.
SRC_ID
TTYPE
Name
VAL
—
—
ECM Error Low Address Capture Register (EELADR)
ADDR
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 7-9. ECM Error Low Address Capture Register (EELADR)
Source ID. Specifies the source device mastering the transaction.
00000 PCI interface
00001 PCI Express 2
00010 PCI Express 1
00011 PCI Express 3
00100 Enhanced local bus
00101 USB1
00110 Reserved
00111 Security
01000 SATA2
01001 USB3
01010 Boot sequencer
01011 eSDHC
01100 Reserved
01101 SATA1
Reserved
Transaction type. Defined as follows:
0000 Write
0001 Reserved
0010 Write with allocate
0011 Write with allocate with lock
0100 Address only transaction
0101–0111Reserved
1000 Read
Reserved
Register data valid.
0 ECM error attribute capture register does not contain valid information.
1 ECM error attribute capture register contains valid information.
Table 7-8. EEATR Field Descriptions (continued)
Address. Specifies the lower-order 32 bits of the 36-bit address of the transaction.
Qualified by EEATR[VAL].
Table 7-9. EELADR Field Descriptions
All zeros
ADDR
Description
Description
01110 Reserved
01111 DDR controller
10000 Processor (instruction)
10001 Processor (data)
10010–10011 Reserved
10100 USB2
10101 DMA
10110 Reserved
10111 SAP
11000 eTSEC1
11001 Reserved
11010 eTSEC3
11010–11111 Reserved
1001 Read with unlock
101x Reserved
1100 Read with clear atomic
1101 Read with set atomic
1110 Read with decrement atomic
1111 Read with increment atomic
Figure
7-9.
Freescale Semiconductor
Access: Read only
31