MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1216

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Serial Peripheral Interface
18.1.1
The major features of the eSPI are listed as follows:
18.1.2
As the eSPI is a character-oriented communication unit, the core is responsible for packing and unpacking
the receive and transmit frames. A frame consists of all of the characters transmitted or received during a
completed eSPI transmission session, from the first character written to the SPITF register to the last
character transmitted with the total number as indicated in the command written to the SPCOM register.
See
The core receives data by reading the eSPI receive data register (SPIRF) when the NE (“not empty”) bit
in the eSPI event register (SPIE) is set.
The core transmits data by writing it into the SPITF. After the core writes the final character to SPITF it
waits for DON bit in the SPIE to be set indicating frame was fully transmitted. It might then write a new
command to SPCOM.
The eSPI sets the NF (“not full”) bit in SPIE whenever its transmit FIFO is not full.
The eSPI core handshake protocol can be implemented by using a polling or interrupt mechanism. When
using a polling mechanism, the core reads the SPIE in a predefined frequency and acts according to the
value of the SPIE bits. The polling frequency depends on the eSPI serial channel frequency. When using
the interrupt mechanism, setting either the TNF (not full) or RNE (not empty) bits of the SPIE causes an
interrupt to the core. The core then reads the SPIE and acts appropriately.
18-2
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Section 18.3.1.4, “eSPI Command Register
Interface contains SPI_MOSI, SPI_MISO, SPI_CLK, and 4 chip selects
Supports eSPI master
Supports RapidS
Full-duplex or half-duplex master operation
Supports Winbond dual output read
Command in transaction level—easier for accessing eSPI devices
Works with a range from 4-bit to 16-bit data characters
Supports back-to-back character transmission and reception
supports reverse data mode for 8/16 bits data characters
Supports single-master environment
Maximum clock rate possible is (system clock rate/4)
Independent programmable baud rate generator
Programmable clock phase and polarity.
Supports 4 different configurations per chip select
Local loopback capability for testing
Supports booting from eSPI interface. See
information.
Features
eSPI Transmission and Reception process
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TM
full clock cycle operation
(SPCOM),” for more information.
Section 4.5.1.2, “eSPI Boot
ROM,” for more detailed
Freescale Semiconductor