MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 269

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.1.6
The ECM error enable register (EEER) shown in
the e500 core through the internal int interrupt signal.
Table 7-7
7.2.1.7
The ECM error attributes capture register (EEATR) is shown in
Table 7-8
Freescale Semiconductor
Offset 0x0_1E08
Reset
0–30
Offset 0x0_1E0C
Reset
8–10
Bits Name
Bits
0–2
3–7
31
W
R
W
R
0
LAEE Local access error enable. Note that a read that attempts to access an unmapped target causes the
0
describes EEER fields.
describes EEATR fields.
BYTE_CNT Byte count. Specifies the transaction byte count.
—
—
Name
—
—
2 3
ECM Error Enable Register (EEER)
ECM Error Attributes Capture Register (EEATR)
Reserved
assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is
disabled (by clearing HID1[RFXE]). If HID1[RFXE] is zero and this error occurs, LAEE must be set to
ensure that an interrupt is generated. For more information, see
the Core Complex Bus
0 Disable reporting local access errors as interrupts.
1 Enable reporting local access errors as interrupts.
BYTE_CNT
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
00000 32 bytes
00001 1 byte
00010 2 bytes
Reserved
Figure 7-8. ECM Error Attributes Capture Register (EEATR)
7 8
Figure 7-7. ECM Error Enable Register (EEER)
—
Table 7-8. EEATR Field Descriptions
(CCB),” and the PowerPC™ e500 Core Family Reference Manual
Table 7-7. EEER Field Descriptions
10 11
SRC_ID
Figure 7-7
15 16 17
—
All zeros
All zeros
Description
—
Description
TTYPE
enables the reporting of error conditions to
00100 4 bytes
01000 8 bytes
10000 16 bytes
Figure
20 21
Section 5.2, “e500 Core Integration and
7-8.
—
e500 Coherency Module
Access: Read only
Access: Read/Write
.”
30
30
LAEE
VAL
31
31
7-7