MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1151

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.8.2.4
The capabilities pointer identifies additional functionality supported by the device.
17.3.8.2.5
The interrupt line register is used by device drivers and OS software to communicate interrupt line routing
information. Values in this register are programmed by system software and are system specific.
Freescale Semiconductor
Offset 0x34
Reset
Offset 0x3C (EP-mode only)
Reset
W
W
R
R
Bits
7–0
0
7
7
Capabilities Pointer
Capabilities Pointer Register—0x34
PCI Express Interrupt Line Register (EP-Mode Only)—0x3C
Bits
7–0
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-53. PCI Express Interrupt Line Register Field Description
Interrupt Line Used to communicate interrupt line routing information.
1
Table 17-52. Capabilities Pointer Register Field Description
Name
Figure 17-54. PCI Express Interrupt Line Register
Figure 17-53. Capabilities Pointer Register
The capabilities pointer provides the offset (0x44) for additional PCI-compatible
registers above the common 64-byte header. Refer to
Compatible Device-Specific Configuration
0
Capabilities Pointer
0
Interrupt Line
All zeros
Description
0
Description
Space,” for more information.
1
Section 17.3.9, “PCI
PCI Express Interface Controller
0
Access: Read/Write
Access: Read only
0
0
0
17-55