MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1131

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
24–31
Bits
11
12
13
14
15
16
17
18
19
20
21
22
23
CDNSCD Completion with data not successful disable. When set disables the setting of
CRSNCD CRS non configuration disable. When set disables the setting of PEX_ERR_DR[CRSNC] bit.
CRSTD
IOIEPD
ICCAD
IACAD
CIEPD
PNMD
OACD
Name
IOISD
IOIAD
MISD
CISD
—
Table 17-25. PCI Express Error Disable Register Field Descriptions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express no map disable. When set disables the setting of PEX_ERR_DR[PNM] bit.
1 Disable no map PCI Express packet detection
0 Enable no map PCI Express packet detection
PEX_ERR_DR[CDNSC] bit.
1 Disable completion with data not successful detection
0 Enable completion with data not successful detection
1 Disable CRS non configuration detection
0 Enable CRS non configuration detection
Invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA configuration access disable. When set
disables the setting of PEX_ERR_DR[ICCA] bit.
1 Disable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access detection
0 Enable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access detection
Invalid ATMU configuration access. When set disables the setting of PEX_ERR_DR[IACA] bit.
1 Disable invalid ATMU configuration access detection
0 Enable invalid ATMU configuration access detection
CRS thresholded disable. When set disables the setting of PEX_ERR_DR[CRST] bit.
1 Disable CRS threshold detection
0 Enable CRS threshold detection
Message invalid size disable. When set disables the setting of PEX_ERR_DR[MIS] bit.
1 Disable invalid outbound message size detection
0 Enable invalid outbound message size detection
I/O invalid size disable. When set disables the setting of PEX_ERR_DR[IOIS] bit.
1 Disable invalid outbound I/O size detection
0 Enable invalid outbound I/O size detection
Configuration invalid size disable. When set disables the setting of PEX_ERR_DR[CIS] bit.
1 Disable invalid outbound configuration size detection
0 Enable invalid outbound configuration size detection
Configuration invalid EP disable. When set disables the setting of PEX_ERR_DR[CIEP] bit.
1 Disable outbound configuration transaction EP mode detection
0 Enable outbound configuration transaction EP mode detection
I/O invalid EP disable. When set disables the setting of PEX_ERR_DR[IOEP] bit.
1 Disable outbound I/O transaction EP mode detection
0 Enable outbound I/O transaction EP mode detection
Outbound ATMU crossing disable. When set disables the setting of PEX_ERR_DR[OAC] bit.
1 Disable outbound crossing ATMU detection
0 Enable outbound crossing ATMU detection
I/O invalid address disable. When set disables the setting of PEX_ERR_DR[IOIA] bit.
1 Disable greater than 4G I/O address detection
0 Enable greater than 4G I/O address detection
Reserved
Description
PCI Express Interface Controller
17-35