MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1320

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Enhanced Secure Digital Host Controller
20.6.2.2
The host consists of three types of reset:
After the card is reset, the host needs to validate the voltage range of the card. See
software flow to reset the eSDHC and card.
20-46
Set IRQSIGEN[CINIEN] to enable card detection interrupt.
When an interrupt from eSDHC is received, check IRQSTAT[CINS] to see if it is caused by card
insertion.
Clear the IRQSIGEN[CINIEN] to disable card detection interrupt and ignore all card insertion
interrupt afterwards.
Hardware reset (card and host) which is driven by POR (power on reset).
Software reset (host only) is proceeded by the write operation on the SYSCTL[RSTD],
SYSCTL[RSTC], or SYSCTL[RSTA] bits to reset the data part, command part, or all parts of the
host controller, respectively.
Card reset (card only). The command CMD0, GO_IDLE_STATE, is the software reset command
for all types of MMCs and SD memory cards. This command sets each card into idle state
regardless of the current card state. The cards are initialized with a default relative card address
(RCA = 0x0000) and with a default driver stage register setting (lowest speed, highest driving
current capability).
Reset
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 20-25. Flow Diagram for Card Detection
Enable card detection IRQ
Wait for eSDHC interrupt
Clear CINIEN to disable
card detection interrupt
Voltage validation
Check CINS bit
Yes, card present
No card present
(1)
(2)
Figure 20-26
Freescale Semiconductor
for the

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