MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 296

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13–15
16–18
DDR Memory Controller
Table 8-12
8-22
9–12
Bits
0–3
4–8
RD_TO_PRE
ADD_LAT
WR_LAT
describes the TIMING_CFG_2 fields.
Name
CPO
—
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Additive latency. The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW].
(DDR2-specific)
0000 0 clocks
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
MCAS-to-preamble override. Defines the number of DRAM cycles between when a read is issued
and when the corresponding DQS preamble is valid for the memory controller. For these decodings,
“READ_LAT” is equal to the CAS latency plus the additive latency.
00000 READ_LAT + 1
00001 Reserved
00010 READ_LAT
00011 READ_LAT + 1/4
00100 READ_LAT + 1/2
00101 READ_LAT + 3/4
00110 READ_LAT + 1
00111 READ_LAT + 5/4
01000 READ_LAT + 3/2
01001 READ_LAT + 7/4
01010 READ_LAT + 2
01011 READ_LAT + 9/4
01100 READ_LAT + 5/2
01101 READ_LAT + 11/4
01110 READ_LAT + 3
01111 READ_LAT + 13/4
Write latency. Note that the total write latency for DDR2 is equal to WR_LAT + ADD_LAT; the write
latency for DDR1 is 1. DDR1 is not supported for the MPC8536E. If a write latency of 1 is desired,
then the additive latency must also be set to at least 1 cycle.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Reserved
Read to precharge (t
ADD_LAT + t
then this field needs to be programmed to (t
000 Reserved
001 1 cycle
010 2 cycles
011 3 cycles
Table 8-12. TIMING_CFG_2 Field Descriptions
RTP
cycles between read and precharge. If DDR_SDRAM_CFG_2[OBC_CFG] is set,
RTP
). For DDR2, with a non-zero ADD_LAT value, takes a minimum of
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
10000 READ_LAT + 7/2
10001 READ_LAT + 15/4
10010 READ_LAT + 4
10011 READ_LAT + 17/4
10100 READ_LAT + 9/2
10101 READ_LAT + 19/4
10110 READ_LAT + 5
10111 READ_LAT + 21/4
11000 READ_LAT + 11/2
11001 READ_LAT + 23/4
11010 READ_LAT + 6
11011 READ_LAT + 25/4
11100 READ_LAT +13/2
11101 READ_LAT + 27/4
11110 READ_LAT + 7
11111 Reserved
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
100 4 cycles
101 5 cycles
110 6 cycles
111 7 cycles
Description
RTP
+ 2 cycles)
Freescale Semiconductor