MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 89

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
12-19
12-20
12-21
12-22
12-23
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
13-26
13-27
13-28
13-29
13-30
13-31
13-32
13-33
13-34
13-35
13-36
Freescale Semiconductor
UDSR Field Descriptions.................................................................................................... 12-17
UDSR[TXRDY] Set Conditions ......................................................................................... 12-18
UDSR[TXRDY] Cleared Conditions.................................................................................. 12-18
UDSR[RXRDY] Set Conditions......................................................................................... 12-18
UDSR[RXRDY] Cleared Conditions ................................................................................. 12-19
Signal Properties—Summary................................................................................................ 13-4
Enhanced Local Bus Controller Detailed Signal Descriptions ............................................. 13-5
Enhanced Local Bus Controller Registers ............................................................................ 13-9
BRn Field Descriptions....................................................................................................... 13-11
Reset value of OR0 Register ............................................................................................... 13-13
Memory Bank Sizes in Relation to Address Mask ............................................................. 13-13
ORn—GPCM Field Descriptions ....................................................................................... 13-14
ORn—FCM Field Descriptions .......................................................................................... 13-17
ORn—UPM Field Descriptions .......................................................................................... 13-20
MAR Field Descriptions ..................................................................................................... 13-21
MxMR Field Descriptions................................................................................................... 13-21
MRTPR Field Descriptions ................................................................................................. 13-23
MDR Field Description....................................................................................................... 13-24
LSOR Field Description...................................................................................................... 13-25
LURT Field Descriptions .................................................................................................... 13-26
LTESR Field Descriptions .................................................................................................. 13-27
LTEDR Field Descriptions.................................................................................................. 13-28
LTEIR Field Descriptions ................................................................................................... 13-29
LTEATR Field Descriptions................................................................................................ 13-31
LTEAR Field Descriptions.................................................................................................. 13-31
LTECCR Field Descriptions ............................................................................................... 13-32
LBCR Field Descriptions.................................................................................................... 13-33
LCRR Field Descriptions.................................................................................................... 13-35
FMR Field Descriptions...................................................................................................... 13-36
FIR Field Descriptions ........................................................................................................ 13-38
FCR Field Descriptions....................................................................................................... 13-38
FBAR Field Descriptions.................................................................................................... 13-39
FPAR Field Descriptions, Small Page Device (ORx[PGS] = 0)......................................... 13-40
FPAR Field Descriptions, Large Page Device (ORx[PGS] = 1)......................................... 13-40
FBCR Field Descriptions .................................................................................................... 13-41
FECCn Field Descriptions .................................................................................................. 13-42
GPCM Read Control Signal Timing ................................................................................... 13-50
GPCM Write Control Signal Timing .................................................................................. 13-52
Boot Bank Field Values after Reset for GPCM as Boot Controller.................................... 13-59
FCM Chip-Select to First Command Timing...................................................................... 13-68
FCM Command, Address, and Write Data Timing Parameters.......................................... 13-69
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Tables
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