MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1700

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Q–R
Processor version (PVR), 23-29
Protocols
PVR (processor version register), see e500 core, registers
Q
Quality of service (QoS), see eTSEC
Queue element transfer descriptor (qTD), see USB interface,
Queue heads, see USB interface, queue heads
R
Random number generator (RNG)
RapidIO controller
READY signal, 4-2, 4-10, 25-23, 25-24
Registers
Index-14
configuration reporting
debug modes summary, 25-3
hard reset, 4-8
output signal states during reset, 3-17
PCI Express, modes of operation, 17-4
reset configuration signals, 3-15
sequence of events, 4-9
PCI, see PCI/PCI-X contoller, bus protocol
overview, 10-155
clocks
AFEU
by acronym (memory-mapped registers)
configuration, control, and status, 2-10–2-14, 4-3
eTSEC1–2 data width, 4-20
eTSEC3 protocol, 4-21
general-purpose (external system)
memory debug select (DDR or LBC), 4-23, 25-3
PCI data bus width, 4-22
PCI debug configuration, 25-3
PCI I/O impedance, 4-22
PCI/PCI-X arbiter configuration, 4-23
PCI/PCI-X, modes of operation, 16-67
PCI-X mode selection, 4-22
global utilities, 23-5, 23-6, 23-8, 23-9, 23-12, 23-13
and READY signal, 4-2, 4-10
queue element transfer descriptor (qTD)
minimum CCB frequency equation, 4-26
data size, 10-90
interrupt control, 10-94
interrupt status, 10-92
key, 10-97
key size, 10-89
mode, 10-89
reset control, 10-91
status, 10-62, 10-91, 10-138, 10-157
see Register Index
configuration—LAD[0:31] (GPPORCR), 4-24
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
context ID, 25-22–25-23
crypto-channel
DDR
DEU
ECM, 7-3
eTSEC, 14-26–14-146
EU assignment status, 10-50
fetch, 10-44
global utilities, 23-5
GPIO, 22-2–22-5
I
ID, 10-54
interrupt
L2 cache/SRAM registers, 6-8–6-25
LBC, 13-10
local access window registers
2
C interface, 11-5
device-specific utilities, 2-13
general utilities, 2-12
programmable interrupt controller (PIC) space, 2-13
configuration, 10-37
general, 10-37
configuration registers, 8-12–8-51
error handling registers, 8-53–8-60
error injection registers, 8-51–8-53
interrupt control, 10-66, 10-115
interrupt status, 10-64, 10-113
IV, 10-117
key, 10-117
key size, 10-61, 10-110
mode, 10-58, 10-109
reset control, 10-62, 10-111
DMA attribute registers, 14-118–14-120
FIFO registers, 14-116–14-118
general control and status registers, 14-26–14-40
hash function registers, 14-115–14-116
lossless flow control registers, 14-120–14-121
MAC registers, 14-74–14-87
MIB registers, 14-87–14-115
receive control and status registers, 14-53–14-70
ten-bit interface registers, 14-135–14-145
transmit control and status registers, 14-40–14-52
POR boot mode status, 23-6
POR debug mode status, 23-12
POR device status, 23-9
POR external system configuration, 23-13
POR I/O impedance status, 23-8
POR PLL status, 23-5
clear, 10-54
mask, 10-50
status, 10-53
attributes registers (LAWAR0–LAWAR7), 2-7
base address registers (LAWBAR0–LAWBAR7), 2-7
Freescale Semiconductor
Index