MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 602

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
11.3.1.5
The I2C data register is shown in
Table 11-8
11-10
2
C Interfaces
Bits
Bits
0–7
6
7
Name
RXAK Received acknowledge. The value of SDA during the reception of acknowledge bit of a bus cycle. If the
Name
DATA
MIF
shows the bit descriptions for I2CDR.
Offset I
Reset
I
2
Module interrupt. The MIF bit is set when an interrupt is pending, causing a processor interrupt request
(provided I2CCR[MIEN] is set). The interrupts for I
sourced by the dual I
0 No interrupt is pending. Can be cleared only by software.
1 Interrupt is pending. MIF is set when one of the following events occurs:
received acknowledge bit (RXAK) is low, it indicates that an acknowledge signal has been received after the
completion of eight bits of data transmission on the bus. If RXAK is high, it means no acknowledge signal has
been detected at the 9th clock.
0 Acknowledge received
1 No acknowledge received
Transmission starts when an address and the R/W bit are written to the data register and the I
performs as the master. A data transfer is initiated when data is written to the I2CDR. The most significant bit
is sent first in both cases. In master receive mode, reading the data register allows the read to occur, but also
allows the I
is available after it is addressed. Note that in both master receive and slave receive modes, the very first read
is always a dummy read.
C Data Register (I2CDR)
W
R
•One byte of data is transferred (set at the falling edge of the 9th clock).
•The value in I2CADR matches with the calling address in slave-receive mode.
•Arbitration is lost.
I
2
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
C1: 0x010
C2: 0x110
0
2
C module to receive the next byte of data on the I2C interface. In slave mode, the same function
Table 11-7. I2CSR Field Descriptions (continued)
2
C controller.
Figure
Figure 11-6. I
Table 11-8. I2CDR Field Descriptions
11-6.
2
C Data Register (I2CDR)
All zeros
DATA
Description
Description
2
C1 and I
2
C2 are combined into one interrupt, which is
Access: Read/Write
Freescale Semiconductor
7
2
C interface