MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 822

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.5
This section describes the MAC registers.
14.5.3.5.1
MACCFG1 is written by the user.
Offset eTSEC1:0x2_4500;
Table 14-43
14-74
Reset
Reset
16–22
1–11
\
Bits
12
13
14
15
W
W
0
R
R
eTSEC3:0x2_6500
Soft_Reset
Reset Rx Fun Reset receive function block. This bit is cleared by default.
Reset Rx MC Reset receive MAC control block. This bit is cleared by default.
Reset Tx Fun Reset transmit function block. This bit is cleared by default.
Reset Tx MC Reset transmit MAC control block. This bit is cleared by default.
Soft_Reset
16
0
Name
describes the fields of the MACCFG1 register.
—
—
MAC Registers
—
MAC Configuration 1 Register (MACCFG1)
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Soft reset. This bit is cleared by default. See
Procedure,”
0 Normal operation.
1 Place the entire MAC in reset except for the host interface.
Reserved
0 Normal operation.
1 Place the receive part of the MAC in reset. This block detects control frames and contains the pause
0 Normal operation.
1 Place the transmit part of the MAC in reset. This block multiplexes data and control frame transfers.
0 Normal operation.
1 Place the receive function in reset. This block performs the receive frame protocol.
0 Normal operation.
1 Place the transmit function in reset. This block performs the frame transmission protocol.
Reserved
22
timers.
It also responds to XOFF PAUSE control frames.
Loop Back
23
Figure 14-39. MACCFG1 Register Definition
for more information on setting this bit.
Table 14-43. MACCFG1 Field Descriptions
Figure 14-39
—
24 25
—
Rx_Flow Tx_Flow
26
describes the definition for the MACCFG1 register.
11
27
All zeros
All zeros
Sync’d Rx EN
Reset Rx MC Reset Tx MC Reset Rx Fun Reset Tx Fun
Description
Section 14.6.3.2, “Soft Reset and Reconfiguring
12
28
Rx_EN
13
29
Sync’d Tx EN
Freescale Semiconductor
14
30
Access: Mixed
Tx_EN
15
31