MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1114

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.3.4
The PCI Express power management command register, shown in
mechanism to allow the PCI Express controller to get back to L0 link state.
The fields of the PCI Express power management command register are described in
17-18
Offset 0x02C
Reset
0–28
Bits
Bits
27
28
29
30
31
29
30
31
W
R
0
SPMES Set PME status. This sets the PME status bit and if PME is enabled (see
PTOMR PME_Turn_Off message request. When set broadcasts a PME turn_off message. This bit should not be
PIONIE
AIOFIE
PIOFIE
EXL2S
ABPIE
Name
Name
PIBIE
—
Figure 17-10. PCI Express Power Management Command Register (PEX_PMCR)
PCI Express Power Management Command Register (PEX_PMCR)
Attention indicator off interrupt enable. When set and PEX_PME_MES_DR[AIOF]=1 generates an
interrupt.
1 Enable attention indicator off message interrupt generation
0 Disable attention indicator off message interrupt generation
Power indicator on interrupt enable. When set and PEX_PME_MES_DR[PION]=1 generates an interrupt.
1 Enable power indicator on message interrupt generation
0 Disable power indicator on message interrupt generation
Power indicator blink interrupt enable. When set and PEX_PME_MES_DR[PIB]=1 generates an interrupt.
1 Enable power indicator blink message interrupt generation
0 Disable power indicator blink message interrupt generation
Power indicator off interrupt enable. When set and PEX_PME_MES_DR[PIOF]=1 generates an interrupt.
1 Enable power indicator off message interrupt generation
0 Disable power indicator off message interrupt generation
Attention button pressed interrupt enable. When set and PEX_PME_MES_DR[ABP]=1 generates an
interrupt.
1 Enable attention button press message interrupt generation
0 Disable attention button press message interrupt generation
Reserved
Power Management Status and Control Register—0x48,” on page 17-70
a PM_PME message upstream. This bit should not be used when in RC mode. This bit is self-clearing.
Exit L2 state. When set exits the link state out of L2/L3 ready state in order to send new requests. The
request is only made when entered_L2/L3 ready state is active. This bit is self-clearing. When the link has
exited L2/L3 ready state, the status bit Exit_L2/L3 ready state is set. This bit should not be used when in
EP mode.
used when in EP mode. This bit is self-clearing
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-11. PEX_PME_MES_IER Field Descriptions (continued)
Table 17-12. PEX_PMCR Field Descriptions
—
All zeros
Description
Description
Figure
17-10, provides software a
for more information) it transmits
Section 17.3.9.3, “PCI Express
28
SPMES EXL2S PTOMR
Freescale Semiconductor
Table
29
Access: Read/Write
17-12.
30
31