MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1460

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.8.2.2
21.8.2.2.1
In order to conserve power, USB controller automatically enters the suspended state when no bus traffic
has been observed for a specified period. When suspended, the USB controller maintains any internal
status, including its address and configuration. Attached devices must be prepared to suspend at any time
they are powered, regardless of if they have been assigned a non-default address, are configured, or neither.
Bus activity may cease due to the host entering a suspend mode of its own. In addition, a USB device shall
also enter the suspended state when the hub port it is attached to is disabled.
The USB controller exits suspend mode when there is bus activity. It may also request the host to exit
suspend mode or selective suspend by using electrical signaling to indicate remote wake-up. The ability
of a device to signal remote wake-up is optional. The USB controller is capable of remote wake-up
signaling. When the USB controller is reset, remote wake-up signaling must be disabled.
21.8.2.2.2
The USB controller moves into the suspend state when suspend signaling is detected or activity is missing
on the upstream port for more than a specific period. After the device controller enters the suspend state,
the DCD is notified by an interrupt (assuming DC Suspend Interrupt is enabled). When the USBSTS[SLI]
(device controller suspend) is set, the device controller is suspended.
DCD response when the device controller is suspended is application specific and may involve switching
to low power operation.
Information on the bus power limits in suspend state can be found in USB 2.0 specification.
21.8.2.2.3
If the USB controller is suspended, its operation is resumed when any non-idle signaling is received on its
upstream facing port. In addition, the USB controller can signal the system to resume operation by forcing
resume signaling to the upstream port. Resume signaling is sent upstream by writing a '1' to the
PORTSC[FPR] (resume bit) while the device is in suspend state. Sending resume signal to an upstream
port should cause the host to issue resume signaling and bring the suspended bus segment (one more
devices) back to the active condition.
21.8.3
The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a
uniquely addressable portion of a USB device that can source or sink data in a communications channel
between the host and the device. The endpoint address is specified by the combination of the endpoint
number and the endpoint direction.
21-126
Managing Endpoints
Suspend/Resume
Suspend Description
Suspend Operational Model
Resume
Before resume signaling can be used, the host must enable it by using the
Set Feature command defined in device framework (Chapter 9) of the USB
2.0 Specification.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Freescale Semiconductor