MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 833

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 14-51
Table 14-55
14.5.3.5.14 MAC Station Address Part 2 Register (MACSTNADDR2)
The MACSTNADDR2 register is written by the user.
MACSTNADDR2 register.
Table 14-56
Freescale Semiconductor
Offset eTSEC1:0x2_4544;
Offset eTSEC1:0x2_4540;
Reset
Reset
W
W
R
R
16–31
8–15
0–7
eTSEC3:0x2_6544
eTSEC3:0x2_6540
Bit
16–23
24–31
Station Address, 2nd Octet
0
Station Address, 6th Octet
0
8–15
0–7
Bit
describes the fields of the MACSTNADDR1 register.
describes the fields of the MACSTNADDR2 register.
shows the MACSTNADDR1 register.
Station Address, 2nd Octet
Station Address, 1st Octet
Station Address, 6th Octet
Station Address, 5th Octet
Station Address, 4th Octet
Station Address, 3rd Octet
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-51. MAC Station Address Part 1 Register Definition
Figure 14-52. MAC Station Address Part 2 Register Definition
Name
Name
—
Table 14-55. MACSTNADDR1 Field Descriptions
Table 14-56. MACSTNADDR2 Field Descriptions
7
7
8
Station Address, 5th Octet
8
Station Address, 1st Octet
This field holds the second octet of the station address. The second
octet (station address bits 8
This field holds the first octet of the station address. The first octet
(station address bits 0
Reserved
This field holds the sixth octet of the station address. The sixth
octet (station address bits 40
This field holds the fifth octet of the station address. The fifth octet
(station address bits 32
This field holds the fourth octet of the station address. The fourth
octet (station address bits 24
This field holds the third octet of the station address. The third
octet (station address bits 16
All zeros
All zeros
Figure 14-52
15 16
15 16
Station Address, 4th Octet
–
7) defaults to a value of 0x0.
–
39) defaults to a value of 0x0.
Description
Description
–
15) defaults to a value of 0x0.
–
–
–
describes the definition for the
47) defaults to a value of 0x0.
31) defaults to a value of 0x0.
23) defaults to a value of 0x0.
Enhanced Three-Speed Ethernet Controllers
23 24
—
Station Address, 3rd Octet
Access: Read/Write
Access: Read/Write
14-85
31
31