MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 21

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
13.3.1.8
13.3.1.9
13.3.1.10
13.3.1.11
13.3.1.12
13.3.1.13
13.3.1.14
13.3.1.15
13.3.1.16
13.3.1.17
13.3.1.18
13.3.1.19
13.3.1.20
13.3.1.21
13.3.1.22
13.3.1.23
13.4
13.4.1
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.1.5
13.4.1.6
13.4.1.7
13.4.1.8
13.4.2
13.4.2.1
13.4.2.2
13.4.2.3
13.4.2.3.1
13.4.2.3.2
13.4.2.3.3
13.4.2.3.4
13.4.2.3.5
13.4.2.4
13.4.2.5
13.4.3
13.4.3.1
13.4.3.1.1
13.4.3.1.2
Freescale Semiconductor
Functional Description................................................................................................. 13-42
Basic Architecture.................................................................................................... 13-43
General-Purpose Chip-Select Machine (GPCM)..................................................... 13-48
Flash Control Machine (FCM) ................................................................................ 13-59
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
UPM Refresh Timer (LURT)............................................................................... 13-25
Transfer Error Status Register (LTESR) .............................................................. 13-26
Transfer Error Check Disable Register (LTEDR)................................................ 13-28
Transfer Error Interrupt Enable Register (LTEIR) .............................................. 13-29
Transfer Error Attributes Register (LTEATR) ..................................................... 13-30
Transfer Error Address Register (LTEAR).......................................................... 13-31
Transfer Error ECC Register (LTECCR)............................................................. 13-31
Local Bus Configuration Register (LBCR) ......................................................... 13-32
Clock Ratio Register (LCRR).............................................................................. 13-34
Flash Mode Register (FMR)................................................................................ 13-35
Flash Instruction Register (FIR) .......................................................................... 13-37
Flash Command Register (FCR) ......................................................................... 13-38
Flash Block Address Register (FBAR)................................................................ 13-39
Flash Page Address Register (FPAR) .................................................................. 13-39
Flash Byte Count Register (FBCR) ..................................................................... 13-41
Flash ECC Blockn Register (FECC0–FECC3) ................................................... 13-41
Address and Address Space Checking ................................................................ 13-43
External Address Latch Enable Signal (LALE) .................................................. 13-43
Data Transfer Acknowledge (TA) ....................................................................... 13-45
Data Buffer Control (LBCTL)............................................................................. 13-46
Atomic Operation ................................................................................................ 13-46
Parity Generation and Checking (LDP)............................................................... 13-47
Bus Monitor ......................................................................................................... 13-47
PLL Bypass Mode ............................................................................................... 13-47
GPCM Read Signal Timing ................................................................................. 13-49
GPCM Write Signal Timing ................................................................................ 13-51
Chip-Select Assertion Timing ............................................................................. 13-52
External Access Termination (LGTA) ................................................................. 13-57
GPCM Boot Chip-Select Operation .................................................................... 13-58
FCM Buffer RAM ............................................................................................... 13-61
Programmable Wait State Configuration......................................................... 13-53
Chip-Select and Write Enable Negation Timing ............................................. 13-53
Relaxed Timing ............................................................................................... 13-54
Output Enable (LOE) Timing .......................................................................... 13-56
Extended Hold Time on Read Accesses .......................................................... 13-56
Buffer Layout and Page Mapping for Small-Page NAND Flash Devices ...... 13-61
Buffer Layout and Page Mapping for Large-Page NAND Flash Devices ...... 13-62
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