MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1015

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.4.1.3
An external control can be used to control all DMA channels by setting MRn[EMS_EN]. The external
control can direct the DMA channel in the following transfer modes:
Note that when operating the DMA in chaining mode the register byte count field, BCR[BC], must be
initialized to zero before enabling the pause feature. In chaining modes, the channel does not pause for
descriptor fetch transfer.
The external control and the DMA controller use a well defined protocol to communicate. The external
control can start or restart a paused DMA transfer. The DMA controller acknowledges a DMA transfer in
progress and also indicates a transfer completion. Note that external control cannot cause a channel to enter
a paused state.
The pause feature can be enabled by setting MRn[EMP_EN]. MRn[BWC] specifies how much data to
allow a specific channel to transfer before entering a paused state by clearing MRn[CS]. Note, however,
that write data for a paused transfer may not have reached the target interface when so indicated. The
channel can be restarted from a paused state by the asserted edge of DREQ as driven by an external master.
In chaining modes, the channel does not pause for descriptor fetch transfer; it only pauses during the actual
data transfer.
The following signals are defined for the external control interface:
Detailed descriptions of the external control interface are in
control interface is shown in
Freescale Semiconductor
4. Initialize the current list descriptor address register to point to the first list descriptor segment in
5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
6. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last
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memory. This write automatically causes the DMA controller to begin the list descriptor fetch and
set MRn[CS].
descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error
occurs during any of the transfers.
Basic direct
Basic chaining
Extended direct
Extended chaining
DMA_DREQ—Asserting edge triggers a DMA transfer start or restart from a pause request. Sets
MRn[CS]. (Note that negating DMA_DREQ does NOT clear MRn[CS].)
DMA_DACK—Indicates a DMA transfer currently in progress. SRn[CB] is set.
DMA_DDONE—Indicates the completion of the DMA controller’s involvement in the transfer
and the readiness to accept a new DMA command. SRn[CB] is clear. Note, however, that write data
may still be queued at the target interface or in the process of transfer on an external interface.
External Control Mode Transfer
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
15-23.
Table
15-3. The timing diagram of the external
DMA Controller
15-29