MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 522

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_8028
Security Engine (SEC) 3.0
Reset
Table 10-39
10.7.2.6
The interrupt status register indicates which unmasked errors have occurred and have generated error
interrupts to the channel. Each bit in this register can only be set if the corresponding bit of the AFEU
interrupt mask register is zero (see
10-92
W
R
59–60
40-47
48-55
56-57
0–39
Bits
0
58
61
62
63
describes AFEU Status Register fields.
AFEU Interrupt Status Register
Name
HALT
OFL
IFL
RD
—
—
—
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-39. AFEU Status Register Field Descriptions
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
Halt. Indicates that the AFEU has halted due to an error.
0 AFEU not halted
1 AFEU halted
Note: Because the error causing the AFEU to stop operating may be masked before
Reserved
Error interrupt: This status bit reflects the state of the error interrupt signal, as sampled by
the controller interrupt status register
(ISR)”).
0 AFEU is not signaling error
1 AFEU is signaling error
Done interrupt: This status bit reflects the state of the done interrupt signal, as sampled by
the controller interrupt status register
(ISR)”).
0 AFEU is not signaling done
1 AFEU is signaling done
Reset Done. This status bit, when high, indicates that AFEU has completed its reset
sequence, as reflected in the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the
reaching the interrupt status register, the AFEU interrupt status register is used to
provide a second source of information regarding errors preventing normal
operation.
register, indicating the EU is ready for operation.
Figure 10-36. AFEU Status Register
Section 10.7.2.7, “AFEU Interrupt Mask
All zeros
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
Description
39 40
OFL
47 48
IFL
Register”).
55 56 57
—
Freescale Semiconductor
HALT
58
Access: Read only
59 60 61 62 63
—
EI DI RD