MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1267

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The four link layer state machines are described in the following sections.
19.5.1.1
The link idle state machine is responsible for detecting a transmit request from the transport layer or a
frame reception request from the far end. The state machine arbitrates whether these two events coincide.
The SATA specification defines that the host end always backs down in this case. Furthermore, this
machine interprets power mode change requests from both the transport and PhyCtrl layers and initiates
actions to enable the power mode change. Power mode change can only occur if the feature is enabled via
the PhyCtrlCfg register LPB_EN bits. Finally, this state machine also detects the negation and assertion of
PHY_READY from the PHY and notifies the transport layer of the change.
19.5.1.2
This state machine is responsible for frame transmission to the PHY. The state machine places the SOF
and EOF headers on each frame, calculates the CRC, and inserts it before the EOF delimiter. Between the
SOF and CRC markers, the link layer accepts the current word from the transport layer and uses this as the
next word of the frame. The link layer also inserts a pair of ALIGN primitives every 254 words of frame
data. Finally, at the end of the frame transmission, the state machine waits for status from the far end link
layer via received R_OK or R_ERR primitives. If the far end received the frame correctly, the local link
layer signals TX_OK to the transport layer; otherwise, it signals TX_NOT_OK to the transport layer.
The transmit state machine also partakes in flow control actions, if necessary, during packet transmission.
If the transport layer cannot supply a new word and the frame is not finished, the transmit state machine
responds by sending HOLD primitives until the transport layer is ready with valid frame data. Also, during
frame transmission, if the state machine detects a received HOLD primitive from the PHY layer, it
interrupts the current frame transmission and sends HOLDA primitives to the PHY to be transmitted to the
far end.
The current frame transmission can only be aborted by two events. The first is on reception of a DMAT
primitive from the far end. In this case, the link layer state machine stops the current transfer and calculates
and inserts the current CRC. This is a controlled termination. The second is when the transport layer wishes
to send a control register frame signaled via TRANSMIT_CRF.
If at any point in the frame transmission process, the link layer detects error conditions, it signals these to
the command layer. The errors can occur if the link layer detects the following conditions:
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Link layer state machines
Frame content scrambler and descrambler
CRC generation and checking
Bus interfaces to PHY and transport layer
CONT primitive processing
ALIGN insertion on transmit
Debug functionality
BIST support
Link layer state machines
Link Idle State Machine
Transmit State Machine
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
SATA Controller
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