MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1309

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Reset
Reset
Offset: 0x050 (FEVT)
FEVTAC12E
FEVTDMAE
FEVTDEBE
FEVTDTOE
FEVTCEBE
FEVTCINT
FEVTDCE
FEVTCCE
FEVTCCE
FEVTCIE
W FEVT
W
R
R
Field
1–2
4–6
10
11
12
13
14
15
0
3
7
8
9
CINT
16
0
0
1
—
Force event card interrupt. Writing 1 to this bit generates a low-level short pulse on the internal
SDHC_DAT[1] line, which imitates a self-clearing interrupt from the external card. If enabled,
IRQSTAT[CINT] is set and the interrupt service routine may treat this interrupt as a normal interrupt from
the external card.
Reserved
Force event DMA error. Forces IRQSTAT[DMAE] to set.
Reserved
Force event Auto CMD12 error. Forces IRQSTAT[AC12E] to set.
Reserved
Force event data end bit error. Forces IRQSTAT[DEBE] to set.
Force event data CRC error. Forces IRQSTAT[DCE] to set.
Force event data time out error. Forces IRQSTAT[DTOE] to set.
Force event command index error. Forces IRQSTAT[CCE] to set.
Force event command end bit error. Forces IRQSTAT[CEBE] to set.
Force event command CRC error. Forces IRQSTAT[CCE] to set.
Force event command time out error. Forces IRQSTAT[CTOE] to set.
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DMAE
FEVT
0
3
—
4
Figure 20-18. Force Event Register (FEVT)
—
Table 20-24. FEVT Field Descriptions
6
AC12E
FEVT
23
0
7
FEVTCNI
BAC12E
—
24
0
8
All zeros
All zeros
Description
DEBE
FEVT
25
0
9
—
FEVT
DCE
10
26
0
FEVTA
DTOE
C12IE
FEVT
11
27
0
0
Enhanced Secure Digital Host Controller
C12EBE
FEVTA
FEVT
CIE
12
28
0
0
C12CE
FEVTA
CEBE
FEVT
13
29
0
0
C12TOE
FEVTA
FEVT
CCE
Access: Write
14
30
0
0
C12NE
FEVTA
CTOE
FEVT
20-35
15
31
0
0