MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 465

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

have internal interrupt masks, but the controller can be programmed to disable channel interrupts through
its interrupt enable register. For more details on interrupt types and disablement, see
“Interrupt Enable, Interrupt Status, and Interrupt Clear Registers (IER, ISR,
10.4.2.1
Channel done interrupt generation depend on the setting of the CDIE (channel done interrupt enable) and
NT (notification type) bits in the channel configuration register (see
Configuration Register
after every successfully completed descriptor; If CDIE is set and NT is cleared, an interrupt is generated
after each successfully completed descriptor with the DN (done notification) bit set in the descriptor’s
header word. If the EU(s) signal any error during processing, the channel done interrupt is not generated.
Even if multiple channel done interrupt events are generated by a channel before the first can be cleared
by the host, the interrupt events are not lost. The controller keeps count of the backlog of channel done
interrupts from each channel (see
10.4.2.2
The channel error interrupt is generated when an error condition occurs during descriptor processing. The
error could be a bus error for a transaction requested by the channel; or it could be in one of the EUs
reserved by the channel, or in the channel itself. The channel error interrupt is asserted as soon as the error
condition is detected. The type of error condition is reflected in the ERROR field of the channel status
register (CSR).
For most error types, the error causes the corresponding channel to halt. Any EUs reserved by the halted
channel continue to be reserved until the channel reset occurs. Other channels continue normal processing,
though they may be held up if they need an EU that is reserved by a halted channel.
Handling of errors depends on the error type. Details of each error type are given in
types, the host must clear the source of the error before restarting the channel. If the channel is halted, the
host restarts it by setting the no-pop-reset, continue or reset bits of the CCR (see
“Channel Configuration Register
10.4.3
The polychannel has several aggregate performance counters, which are common to all channels; plus a
set of channel-specific registers, descriptor buffers, and link tables which are duplicated for each channel.
The following subsections describes the format and function of all of these objects in the SEC’s memory.
10.4.3.1
The SEC maintains several counters, which are described in the following subsections.
10.4.3.1.1
The fetch FIFO enqueue counter, shown in
that have been enqueued to the channel fetch FIFOs.
Freescale Semiconductor
Polychannel Registers
Channel Done Interrupt
Channel Error Interrupt
Traffic Counters
Fetch FIFO Enqueue Counter
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(CCR)”). If both CDIE and NT are set, the channel generates an interrupt event
(CCR)”).
Section 10.5.3, “Controller
Figure
10-7, counts the total number of descriptor addresses
Interrupts”).
Section 10.4.4.1, “Channel
ICR).”
Section 10.4.4.1,
Table
Security Engine (SEC) 3.0
Section 10.5.4.2,
10-15. For some
10-35