MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 753

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3
The eTSEC’s primary operational modes are the following:
Freescale Semiconductor
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Ethernet and FIFO operation
The ECNTRL register’s FIFO mode enable bit (ECNTRL[FIFM]) allows bypass of the Ethernet
MAC and enables I/O through the FIFO interface sharing the normal GMII signals. Each eTSEC
supports an 8-bit FIFO interface independently. If configured in FIFO mode, the FIFOCFG register
determines operation. In FIFO mode data is transferred synchronously with respect to the external
data clock. See the device hardware specifications document for maximum supported frequencies.
Full- and half-duplex operation
This is determined by the MACCFG2 register’s full-duplex bit (MACCFG2[Full Duplex]).
Full-duplex mode is intended for use on point-to-point links between switches or end node to
switch. Half-duplex mode is used in connections between an end node and a repeater or between
repeaters.
If configured in half-duplex mode (10- and 100-Mbps operation; MACCFG2[Full Duplex] is
cleared), the MAC complies with the IEEE CSMA/CD access method.
If configured in full-duplex mode (10/100/1000 Mbps operation; MACCFG2[Full Duplex] is set),
the MAC supports flow control. If flow control is enabled, it allows the MAC to receive or send
PAUSE frames.
10- and 100-Mbps MII interface operation
The MAC–PHY interface operates in MII mode by setting MACCFG2[I/F Mode] = 01. The MII
is the media-independent interface defined by the 802.3 standard for 10/100 Mbps operation. The
speed of operation is determined by the TSECn_TX_CLK and TSECn_RX_CLK signals, which
are driven by the transceiver. The transceiver either auto-negotiates the speed, or it may be
controlled by software using the serial management interface (MDC/MDIO signals) to the
transceiver.
Clause 22.2.4 of the IEEE 802.3 specification describes the MII management interface.
10- and 100-Mbps RMII interface operation
The RMII is the reduced media-independent interface defined by the RMII Consortium (March
1998) for 10/100 Mbps operation. The speed of operation is determined by the TSECn_TX_CLK
signal, which is driven by the transceiver.
1000 Mbps GMII and TBI interface operation
The MAC–PHY interface operates in GMII mode by setting MACCFG2[I/F Mode] = 10. The
GMII is the gigabit media-independent interface defined by the 802.3 standard for 1000-Mbps
operation.
Independently, the MAC-PHY interface can also operate in TBI mode. Note that either the TBI or
GMII interface is chosen, not both at the same time. TBI is the 10-bit interface which contains PCS
functions (10-bit encoding/decoding) as defined by the 802.3 standard.
In reduced-pin count mode (RGMII or RTBI), the MAC remains configured in GMII or TBI but
the eTSEC muxes and decodes the input signals and provides the MAC with the expected interface.
eTSEC provides the TSECn_GTX_CLK to the PHY in either GMII or TBI mode of operation.
MAC address recognition options
Modes of Operation
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Enhanced Three-Speed Ethernet Controllers
14-5