MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 794

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.2.3
This register defines the default value for the VLAN Ethertype and control word when VLAN tags are
automatically inserted by the eTSEC, and no per-frame VLAN data is supplied by software. On receive,
this register defines a customizable VLAN Ethertype for automatic deletion. Note that an Ethertype of
0x8808 (Control Word) is not permitted as a custom VLAN tag. Frames with an Ethertype of 0x8808 are
dropped by the receiver. In the case of frames containing stacked VLAN tags, this register defines the tag
associated with the outer or metropolitan area VLAN.
Table 14-18
14-46
16–18
20–31
24–31
0–15
Bits
Bits
19
23
Offset eTSEC1:0x2_4108;
Reset 1
W
R
Name
eTSEC3:0x2_6108
Name
TAG
TXF7 Transmit frame event occurred on ring 7. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting
PRI
CFI
VID
0
—
0
describes the fields of the DFVLAN register.
This is the default Ethertype used to tag VLAN frames. On transmit, this tag is inserted ahead of the VLAN
control word; TAG should be set to 0x8100 for IEEE 802.1Q VLAN. On receive, an Ethertype matching TAG or
an Ethertype of 0x8100 marks a VLAN-tagged frame.
Note that if using DFVLAN to set a custom ethertype (that is, using a value other than 0x8100), packets
received with a custom tag are not counted by any of the RMON counters. Affected counters include TRMGV,
RMCA, RBCA, RXCF, RXPF, RXUO, RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF.
This is the default value used for the IEEE Std. 802.1Q canonical format indicator.
This is the default value used for the virtual-LAN identifier in VLAN-tagged frames. A value of zero is defined
as the null VLAN, however field PRI may be still set independently.
This is the default value used for the IEEE Std. 802.1p frame priority.
Default VLAN Control Word Register (DFVLAN)
0
a frame from this ring.
Reserved
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
0
Table 14-17. TSTAT Field Descriptions (continued)
1
TAG
Figure 14-13. DFVLAN Register Definition
Table 14-18. DFVLAN Field Descriptions
0
0
0
0
0
0
0
15 16
0
Description
Figure 14-13
Description
0
PRI
0
18
0
CFI
19
0
describes the DFVLAN register.
20
0
0
0
0
0
Freescale Semiconductor
0
VID
0
Access: Read/Write
0
0
0
0
31
0