MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 410

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.3.7
The interrupt source configuration registers control the source and destinations of interrupts, specifying
parameters such as the interrupting event, signal polarity, and relative priority.
Figure 9-36
Note the following:
9-40
3–29
Bits Name
30
31
Message signaled
•
•
interprocessor
The global timer and interprocessor destination register support only the P0 and P1 options. That
is, they cannot be routed to cint or to IRQ_OUT.
Only the global timer and interprocessor interrupts are multicasting, so only these interrupts allow
more than one destination bit to be specified.
Global timer
P1
P0
—
Messaging
Interrupt Source
External
Internal
Interrupt Source Configuration Registers
shows the destination registers.
Reserved, should be cleared.
Processor core 1. Indicates whether processor core 1 receives the interrupt through int.
0 Processor core 1 does not receive this interrupt.
1 Directs the interrupt to processor core 1 through the assertion of int1 .
Note: Reserved in single-processor implementations.
Processor core 0. Indicates whether processor core 0 receives the interrupt.
0 Processor core 0 does not receive this interrupt.
1 Directs the interrupt to processor core 0 through the assertion of int0 .
The default destination is for processor core 0 to receive this shared message signaled interrupt after the PIC is
reset.
(Section
(Section
(Section
(Section
(Section
(Section
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
9.3.7.2)
9.3.7.4)
9.3.6.5)
9.3.7.6)
9.3.2.5)
9.3.8.1)
Table 9-37. MSIDR n Field Descriptions (continued)
Figure 9-36. Destination Register Summary
W
W
R
R
1
EP CI0 CI1
0
Reserved in single-processor implementations.
1
2
1
3
Description
—
—
Freescale Semiconductor
29
P1
P1
30
1
1
P0
P0
31