MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 476

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.5
All transfers between the hosts and the EUs are moderated by the controller. Some of the main functions
of the controller are as follows:
The remainder of this section discusses the controller’s bus management, arbitration, interrupts, and
registers.
10.5.1
As shown in
bus is a private 64-bit slave bus, with the controller block as the sole master. The SoC’s system bus actually
refers to two buses: a slave bus and a master bus, for which SEC’s controller operates as slave and master,
respectively. All accesses to SEC over the system bus go through the controller.
As mentioned in
depending on whether the SEC’s controller is slave or master. These two modes of access (host-controlled
and channel-controlled) are discussed in the following subsections.
10.5.1.1
For host-controlled access, the host uses the SoC’s slave bus to access the controller as a slave, and the
controller relays the read or write accesses over the internal bus to the appropriate registers and FIFOs of
the EUs. When a write command is received from the system bus, the controller takes the data and sends
10-46
Offset Channel 1: 0x3_11c0-0x3_11df (Gather); 0x3_11e0-0x3_11ff(Scatter)
Reset
Reset
W
W
•
•
•
•
•
R
R
Channel 2: 0x3_12c0-0x3_12df (Gather); 0x3_12e0-0x3_12ff (Scatter)
Channel 3: 0x3_13c0-0x3_13df (Gather); 0x3_13e0-0x3_13ff (Scatter)
Channel 4: 0x3_14c0-0x3_14df (Gather); 0x3_14e0-0x3_14ff (Scatter)
32
0
Accept and execute commands from the slave system bus to read or write memory-mapped
locations (up to 64 bits) anywhere in the SEC.
Accept and execute requests from the polychannel to transfer blocks of bytes among system
memory, EUs, and the channels.
Arbitrate between channels when they contend for EUs and bus access
Realign read and write data to the proper byte alignment
Monitor interrupts from channels and pass them to the host
Controller
Bus Transfers
Figure
Host-Controlled Access
Figure 10-15. Gather/Scatter Link Table Entry Format and Memory Ranges
Section 10.1.3, “Controller
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-1, the SEC has an internal bus and connects to the SoC’s system bus. The internal
SEGLEN
Overview”, there are two modes of access to the SEC,
Not reset
SEGPTR
Not reset
15 16
—
21 22 23 24
R N
Freescale Semiconductor
—
Access: Read/Write
27 28
EPTR
31
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