MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 757

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14.4.1
Below is a description of the eTSEC interface signals. For RGMII mode details please refer to the
Hewlett-Packard reduced gigabit media-independent interface (RGMII) specification version 1.2a, dated
9/22/2000. RMII mode details follow the RMII Consortium Specification, dated 3/20/1998. All other
modes follow the IEEE 802.3 standard, 2000 Edition. Input signals not used are internally disabled. Except
for TSECn_GTX_CLK, output signals not used are driven low.
Freescale Semiconductor
SD2_REF_CLK
SD2_REF_CLK
Signal Name
TSEC_1588_
TSEC_1588_
SD2_RX[0:1]
SD2_RX[0:1]
SD2_TX[0:1]
SD2_TX[0:1]
TRIG_OUT0
TRIG_OUT1
Detailed Signal Descriptions
Table 14-1. eTSEC n Network Interface Signal Properties (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1588—Timer alarm 0
Timer current time is equal to or greater than alarm time comparator register. User
reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external
output pin).
1588—Timer alarm 1
Timer current time is equal to or greater than alarm time comparator register. User
reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external
output pin).
SGMII transmit data (and complement)
SGMII receive data (and complement)
SGMII SerDes2 PLL reference clock (and complement)
Function
Enhanced Three-Speed Ethernet Controllers
Reset
State
0
0
14-9

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