MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1479

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

H-frame and B-frame boundaries with the exception that an asynchronous transfer can not babble through
the SOF (start of B-frame 0).
21.9.1.5.2
The start and complete split operational model differs from EHCI slightly because there is no bus medium
between the EHCI controller and the embedded transaction translator. Where a start or complete-split
operation would occur by requesting the split to the HS hub, the start/complete split operation is simple an
internal operation to the embedded transaction translator.
handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic.
21.9.1.5.3
The following Universal Serial Bus Revision 2.0 Specification items are implemented in the embedded
transaction translator:
21.9.1.5.4
The following Universal Serial Bus Revision 2.0 Specification items are implemented in the embedded
transaction translator:
Freescale Semiconductor
•
•
•
•
USB 2.0–11.17.3
— Sequencing is provided and a packet length estimator ensures no full-speed/low-speed packet
USB 2.0–11.17.4
— • Transaction tracking for 2 data pipes.
USB 2.0–11.17.5
— • Clear_TT_Buffer capability provided
USB 2.0–11.18.6.[1-2]
— Abort of pending start-splits
— Abort of pending complete-splits
Start-Split: All asynchronous buffers full
Start-Split: All periodic buffers full
Start-Split: Success for start of Async. Transaction
Start-Split: Start Periodic Transaction
Complete-Split: Failed to find transaction in queue
Complete-Split: Transaction in Queue is Busy
Complete-Split: Transaction in Queue is Complete
babbles into SOF time.
– EOF (and not started in microframes 6)
– Idle for more than 4 microframes
Split State Machines
Asynchronous Transaction Scheduling and Buffer Management
Periodic Transaction Scheduling and Buffer Management
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Condition
Table 21-96. Emulated Handshakes
Table 21-96
[Actual Handshake from FS/LS device]
Emulate TT Response
No Handshake (Ok)
Bus Time Out
summarizes the conditions where
NYET
ERR
NAK
ACK
Universal Serial Bus Interfaces
21-145