MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 893

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.4.3.10 TBI Control Register (TBICON)
Figure 14-131
Offset 0x11
Table 14-141
Freescale Semiconductor
Reset
12–15
Bits
4–6
8–9
10
11
0
1
2
3
7
W
R
Soft_Reset
Disable Rx Dis Disable receive disparity. This bit is cleared by default.
Disable Tx Dis Disable transmit disparity. This bit is cleared by default.
Clock Select Clock select. This bit is cleared by default.
Soft_Reset
AN Sense
0
MI Mode
0
Name
—
—
—
—
describes the fields of the TBICON register.
describes the definition for the TBICON register.
—
0
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Soft reset. This bit is cleared by default.
0 Normal operation.
1 Resets the functional modules in the TBI.
Reserved. (Ignore on read)
0 Normal operation.
1 Disables the running disparity calculation and checking in the receive direction.
0 Normal operation.
1 Disables the running disparity calculation and checking in the transmit direction.
Reserved
Auto-negotiation sense enable. This bit is cleared by default.
0 IEEE 802.3z Clause 37 behavior is desired, which results in the link not completing.
1 Allow the auto-negotiation function to sense either a Gigabit MAC in auto-negotiation bypass mode
Reserved
0 Allow the TBI to accept dual split-phase 62.5 MHz receive clocks.
1 Configure the TBI to accept a 125 MHz receive clock from the SerDes/PHY. The 125 MHz clock must
This bit describes the configuration mode of the TBI. The user reads a 1 while the TBI is configured in
GMII/MII mode (connected to a GMII/MII PHY) and a 0 while configured in TBI mode (connected to a
1000BASE-X SerDes). Its value is the inverse of ECNTRL[TBIM].
0 TBI mode.
1 GMII mode.
Reserved
Disable
Rx Dis
or an older Gigabit MAC without auto-negotiation capability. If sensed, auto-negotiation complete
becomes true; however, the page received is low, indicating no page was exchanged. Management
can then act accordingly.
be physically connected to ‘PMA receive clock 0’ if using a parallel (non-SGMII) Ethernet protocol.
0
2
Disable
Tx Dis
Figure 14-131. TBI Control Register Definition
0
3
Table 14-141. TBICON Field Descriptions
0
4
—
0
0
6
Sense
AN
7
0
Description
0
8
—
0
9
Enhanced Three-Speed Ethernet Controllers
Select
Clock
10
0
Mode
MII
11
1
12
0
13
0
Access: Mixed
—
14
0
14-145
15
0