MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 894

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6
14.6.1
This section describes how to connect the eTSEC to various interfaces: MII, GMII, RMII, RGMII, TBI,
and RTBI. To avoid confusion, all of the buses follow the bus conventions used in the IEEE 802.3
specification because the PHYs follow the same conventions. (For instance, in the bus TSECn_TXD[7:0],
bit 7 is the msb and bit 0 is the lsb). If a mode does not use all input signals available to a particular eTSEC,
those inputs that are not used must be pulled low on the board.
14.6.1.1
This section describes the media-independent interface (MII) intended to be used between the PHYs and
the eTSEC.
establish eTSEC module connection with a PHY.
An MII interface has 18 signals (including the MDC and MDIO signals), as defined by the IEEE 802.3u
standard, for connecting to an Ethernet PHY.
14.6.1.2
This section describes the reduced media-independent interface (RMII) intended to be used between the
PHYs and the GMII MAC. The RMII is a reduced-pin alternative to the IEEE 802.3u MII. The RMII
reduces the number of signals required to interconnect the MAC and the PHY from a maximum of 18
14-146
1
Functional Description
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’ connections
in the system, assuming that each PHY has a different management address.
eTSEC
Connecting to Physical Interfaces on Ethernet
Figure 14-132
Media-Independent Interface (MII)
Reduced Media-Independent Interface (RMII)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
depicts the basic components of the MII including the signals required to
Receive Data Valid (TSECn_RX_DV)
Carrier Sense Output (TSECn_CRS)
Transmit Enable (TSECn_TX_EN)
Transmit Clock (TSECn_TX_CLK)
Receive Clock (TSECn_RX_CLK)
Transmit Data (TSECn_TXD[3:0])
Receive Data (TSECn_RXD[3:0])
Management Data Clock1 (MDC)
Figure 14-132. eTSEC-MII Connection
Transmit Error (TSECn_TX_ER)
Receive Error (TSECn_RX_ER)
Management Data I/O1 (MDIO)
Collision Detect (TSECn_COL)
Ethernet
10/100
PHY
Freescale Semiconductor
Medium