MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1422

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
The periodic frame list is effectively the leaf level a binary tree, which is always traversed leaf to root.
Each level in the tree corresponds to a 2
on the USB by spreading interrupt queue heads that have the same poll rate requirement across all the
available paths from the frame list. For example, system software can schedule eight poll rate 8 queue
heads and account for them once in the high-speed bus bandwidth allocation.
When an endpoint is allocated an execution footprint that spans a frame boundary, the queue head for the
endpoint must be reachable from consecutive locations in the frame list. An example would be if 8
such an endpoint. Without additional support on the interface, to get 8
software would have to link 8
same path as 4
technique.
FSTN data structures are used to preserve the integrity of the binary-tree structure and enable the use of
the spreading technique.
hardware and software operational model requirements for using FSTNs.
The following queue head fields are initialized by system software to instruct the host controller when to
execute portions of the split-transaction protocol.
21-88
•
•
SplitXState. This is a single bit residing in the Status field of a queue head
is used to track the current state of the split transaction.
Frame S-mask. This is a bit-field where-in system software sets a bit corresponding to the
micro-frame (within an H-Frame) that the host controller should execute a start-split transaction.
This is always qualified by the value of the SplitXState bit in the Status field of the queue head.
For example, referring to
indicating that if the queue head is traversed by the host controller, and the SplitXState indicates
Do_Start, and the current micro-frame as indicated by FRINDEX[2–0] is 0, then execute a
start-split transaction.
Figure 21-53. General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading
Frame List
0
. This upsets the integrity of the binary tree and disallows the use of the spreading
Periodic
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 21.5.7, “Periodic Frame Span Traversal Node (FSTN),”
1
to 8
Figure
•
•
•
0b
. It would then have to move 4
N
21-52, case one, the S-mask would have a value of 0b0000_0001
poll rate. Software can efficiently manage periodic bandwidth
87
86
85
84
83
82
81
80
Level 8
80b
Linkage repeats every 8 for
remainder of frame list
Level 4
43
42
41
40
1
Level 2
and everything linked after into the
0b
21
20
reachable at the correct time,
10
Level 1
(Root)
(Table
Freescale Semiconductor
• • •
21-53). This bit
defines the
0b
were