MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 487

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6
The SEC may be disabled by setting DEVDISR[SEC] in the SoC. The clocks to the SEC are active by
default. The SEC should not be enabled/disabled during normal operation.
SEC disablement is delayed if the disable request is made while descriptors are being processed. Once
notified of the disable request, the SEC channels complete their current tasks, and then are forced to idle
(with no additional reads from the fetch descriptor FIFO). Once all channels are idle, then SEC permits
disablement.
10.7
Execution unit (EU) is the term used for a functional block that performs the mathematical manipulations
required by cryptographic processing. The following execution units are used in the SEC (covered here in
alphabetical order):
Working together, the EUs can perform high-level cryptographic tasks, such as IPsec Encapsulating
Security Protocol (ESP) and digital signature. The remainder of this chapter provides details about these
execution units, including modes of operation, status and control registers, and FIFOs.
10.7.1
This section contains details about the Advanced Encryption Standard Execution Unit (AESU), including
modes of operation, status and control registers, and FIFOs.
Freescale Semiconductor
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Advanced Encryption Standard Execution Unit (AESU) implementing the Rijndael symmetric key
cipher.
ARC4 Execution Unit (AFEU)
Cyclical Redundancy Check Unit (CRCU)
Data Encryption Standard Execution Unit (DEU)
Kasumi (f8/f9) Execution Unit (KEU)
Message Digest Execution Unit (MDEU)
Public Key Execution Unit (PKEU)
Random Number Generator Unit(RNGU)
Power Saving Mode
Execution Units
Advanced Encryption Standard Execution Unit (AESU)
Most of the registers described in this section are not accessed by the host
under normal operation. They are documented here mainly for debug
purposes. Normally the AESU is used through channel-controlled access, so
that most reads and writes of AESU registers are directed by the SEC
channels. Driver software performs host-controlled register accesses only
on a few registers for initial configuration and error handling.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Security Engine (SEC) 3.0
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