MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 729

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MxMR[AM] = 000
MxMR[AM] = 001
MxMR[AM] = 010
MxMR[AM] = 011
MxMR[AM] = 100
MxMR[AM] = 101
MxMR[AM] = 110
MxMR[AM] = 111
Note that any change to the AMX field from one RAM word to the next RAM word executed results in an
address phase on the {LADn, LAn} bus with the assertion of LALE for the number of cycles set for LALE
in the ORn and LCRR registers. The LGPL[0:5] signals maintain the value specified in the RAM word
during the LALE phase.
13.4.4.4.8
When a read access is handled by the UPM, and the UTA bit is 1 (data is to be sampled by the eLBC), the
value of the DLT3 bit in the same RAM word, in conjunction with MxMR[GPL4], determines when the
data input is sampled by the eLBC as follows:
Freescale Semiconductor
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 00
AMX = 10
AMX = 10
(Row)
(Row)
(Row)
(Row)
(Row)
(Row)
•
(Col)
(Col)
(Col)
(Col)
(Col)
(Col)
If MxMR[GPL4] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM word, data is
latched on the falling edge of the bus clock instead of the rising edge. The eLBC samples the data
on the next falling edge of the bus clock, which is during the middle of the current bus cycle. This
msb
0
AMX must not change values in any RAM word which begins a loop.
Data Valid and Data Sample Control (UTA)
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
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3
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4
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5
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6
Table 13-42. UPM Address Multiplexing
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7
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8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTE
Internal Transaction Address
Reserved
Reserved
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23 24 25 26 27 28 29 30
Enhanced Local Bus Controller
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13-87
lsb
31
31
31
31
31
31
31