MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1288

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20-14
SDHC_CD
WPSPL
BWEN
16–19
BREN
Field
CINS
12
13
14
15
20
21
Write protect switch pin level. The write protect switch is supported for memory and combo cards.This bit reflects
the SDHC_WP pin of the card socket. A software reset does not affect this bit. The reset value is affected by the
external write protect switch.
If the SDHC_WP pin is not used but is exposed to pins (PMUXCR[SDHC_WP]=1), it should be tied to a value such
that write is enabled (0 if GENCFGR[SDHC_WP_INV]=0 or 1 if GENCFGR[SDHC_WP_INV]=1). If the SDHC_WP
pin is not exposed to pins (PMUXCR[SDHC_WP]=0), then the value of the SDHC_WP pin does not affect this
register field. However, if eSDHC write functionality is required, then in this case GENCFGR[SDHC_WP_INV]
should be set to 1.
See
0 Write protected (SDHC_WP = 1 if GENCFGR[SDHC_WP_INV]=0 or SDHC_WP = 0 if
1 Write enabled (SDHC_WP = 0 if GENCFGR[SDHC_WP_INV]=0 or SDHC_WP = 1 if
Card detect pin level. This bit reflects the inverse value of the SDHC_CD pin for the card socket. Debouncing is not
performed on this bit. This bit may be valid, but it is not guaranteed because of a propagation delay. Use of this bit
is limited to testing since it must be debounced by software. A software reset does not affect this bit. Write to the
force event register does not affect this bit. If PMUXCR[SDHC_CD]=1, the reset value of this field is affected by the
external card detection pin; if this bit is not used, it should be tied to 0. If PMUXCR[SDHC_CD]=0, this field is
unaffected by the external card detect pin, and will permanently indicate that a card is present.
0 No card present (SDHC_CD = 1) and PMUXCR[SDHC_CD]=1)
1 Card present (SDHC_CD = 0 or PMUXCR[SDHC_CD]=0)
Reserved
Card inserted. Indicates if a card has been inserted. The eSDHC debounces this signal so that the host driver does
not need to wait for it to stabilize. Changing from 0 to 1 generates a card-insertion interrupt in the interrupt status
register and changing from 1 to 0 generates a card removal interrupt in the interrupt status register. A write to the
force event register does not affect this bit.
The software reset for all in the system control register does not affect this bit. A software reset does not affect this
bit.
0 Power-on-reset or no card
1 Card inserted
Reserved
Buffer read enable. This status is used for non-DMA read transfers. The eSDHC may implement multiple buffers to
transfer data efficiently. This read-only flag indicates that a burst-length of valid data exists in the host-side buffer.
When the buffer is read, this bit is cleared. When a burst length of data is ready in the buffer, this bit is set and a
buffer read ready interrupt is generated (if the interrupt is enabled).
0 Buffer read disable
1 Buffer read enable
Buffer write enable. This status is used for non-DMA write transfers. The eSDHC can implement multiple buffers to
transfer data efficiently. This read-only flag indicates if space is available for a burst length of write data.
When the buffer is written, this bit is cleared. When a burst length of data is written to the buffer, this bit is set and a
buffer write ready interrupt is generated (if the interrupt is enabled).
0 Buffer write disable
1 Buffer write enable
GENCFGR[SDHC_WP_INV]=1)
GENCFGR[SDHC_WP_INV]=1 or PMUXCR[SDHC_WP]=0 and GENCFGR[SDHC_WP_INV]=1).
Section 23.4.1.8, “General Configuration Register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-11. PRSSTAT Field Descriptions (continued)
Description
(GENCFGR),” for information on the SDHC_WP_INV bit.
Freescale Semiconductor