MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 669

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13-16
Freescale Semiconductor
10–11
13–29
Bits
3–4
6–7
12
30
31
0
1
2
5
8
9
ATMW Atomic error write
Name
ATMR Atomic error read
UCC
FCT
PAR
BM
WP
CS
CC
—
—
—
—
describes LTESR fields.
Bus monitor time-out
0 No local bus monitor time-out occurred.
1 Local bus monitor time-out occurred. No data beat was acknowledged on the bus within
FCM command time-out
0 No FCM command time-out occurred.
1 A CW0, CW1, CW2, or CW3 command issued to FCM timed-out with respect to the timer configured by
Parity or ECC error
0 No local bus parity error
1 Local bus parity error (GPCM or UPM), or uncorrectable ECC error (FCM). LTEATR[PB] indicates the byte
Reserved
Write protect error
0 No write protect error occurred.
1 A write was attempted to a local bus memory region that was defined as read-only in the memory
Reserved
0 No atomic write error occurred.
1 The subsequent write (WARA) to a memory bank did not occur within 256 bus clock cycles.
0 No atomic read error occurred.
1 The subsequent read (RAWA) to a memory bank did not occur within 256 bus clock cycles.
Reserved
Chip select error
0 No chip select error occurred.
1 A transaction was sent to the eLBC that did not hit any memory bank.
Reserved
UPM Run pattern (MxMR[OP]=11) command completion event
0 No UPM Run pattern operation in progress, or operation pending.
1 UPM Run pattern operation has completed, allowing software to continue processing of results.
FCM command completion event
0 No FCM operation in progress, or operation pending.
1 FCM operation has completed, allowing software to continue processing of results.
LBCR[BMT] x LBCR[BMTPS] bus clock cycles from the start of a transaction.
FMR[CWTO].
lane that caused the error and LTEATR[BNK] indicates which memory controller bank was accessed.
controller. Usually, in this case, a bus monitor time-out will occur (as the cycle is not automatically
terminated).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 13-16. LTESR Field Descriptions
Description
Enhanced Local Bus Controller
13-27